| With the continuous development of integrated circuits,the shrinking feature size and the process enters the deep-nano level.In the 7-nanometer process,chip interconnects are more and more complex,interconnect lines are getting thinner and thinner,and net delay becomes an important part of timing analysis.The number of metal layers exceeds 12 layers,and the clock tree structure is difficult to balance.In addition,crosstalk,IR-drop,congestion and power consumption have all become issues have to face for back-end design.The achievement of the paper are as follows:1)Research on the type of clock.Through the research of clock latency,clock skew and clock uncertainty,as well as the research of various clock trees and the related configuration of clock tree synthesis to research the clock tree synthesis.And the clock is transmitted by using H-tree from the top layer to the sub-module,and then use the clock mesh in the M12 layer of the sub-module to complete the CTS stage for the sub-module.2)Research on the design rules for the 7-nanometer process.In the process of layout planning,through the research of the connection between the macro and the connection with the ports,the placement of the macro is completed;through the research of manufacturing problems such as antenna and the performance of new cells,the placement of physical cells is completed;power planning was completed through the study of macro and standard cells.In the process of place,course placement firstly,then legalization,optimize the timing and congestion,and then used multiple optimization methods to optimize the result multiple times,and also optimize the power consumption by using amulti-bit banking technology.In the process of CTS,the use of clock gating technology optimizes the power consumption of the clock and greatly reduces power consumption.In the process of route,multiple iterations are used to iterate through the results of the route to optimize the routing results.In the ECO stage,the physical rules under 7 nanometers are studied,DRC,formality and LVS are performed on the sub-modules,and the problems are repaired with the new physical rules under 7 nanometers.Research on the method of STA under 7 nanometer process.Research on a new method which named MCMM.Research on OCV,in order to avoid excessive pessimism caused by OCV,a new AOCV model was studied to simulate the influence of process variation on timing in the chip.Using the new OCV model and MCMM analysis method to analyze the timing violations under the 7-nm process,propose solutions and implement them in a targeted manner.Research on the power consumption of the chip.And adopt clock gating technology and other technology to reduce the power consumption of the chip.The IR-drop problem and EM problem appearing under the 7-nanometer process were researched,and an improved scheme was proposed for the problem.The dynamic IR-drop of the chip was tested by redhawk to verify the scheme.In this paper,a new manufacturing process,a double-pattern process,is studied.The lithography under the 7-nm process is completed by this process,and the physical rule characteristics under the process are studied.In this paper,the divergence study is carried out for the problem that the clock source latency is too large and can't meet the expected expectations during the CTS.Two new schemes are proposed to impose more constraints and interventions on the position of the cells during the CTS.Through comparative analysis,determine the program category,and use the automated tcl(tool command language)to implement and complete the automation solution.It has been verified that the clock source latency can be reduced by 8.8% after the implementation of the scheme.The final back-end design results show that the maximum frequency of the sub-modules designed in this paper reaches 2.27 GHz,the scale reaches 430,000 gates,and the size is 238412.1398 square micrometers.In this sub-modules,timing closure,meet the physical rules under the 7-nm process,DRC and LVS is clean,meet standards of sign off. |
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