Physical Design And Research Of Universal Memory Controller IP Core

With the rapid development of integrated circuits,the process feature size of the chip has been reduced to the nano level,which is bringing many new challenges.The increase of frequency and multi-mode multi-corner increase the complexity of timing closure.Physical verification becomes difficult due to the small size,and the power consumption problem becomes more and more important.Therefore,the new physical design problems are studied in this thesis.This design is based on the GF 14 nm Fin FET process and uses the Synopsys series of tools to perform logic synthesis and physical design of general-purpose memory control modules in the AMD Vega GPU.There are about 779,000 cells in this digital modules.It is used to control SDRAM read and write data in display module and memory module.The paper mainly completes the module level logic synthesis,P&R,static timing analysis and ECO four parts,including PR floorplan,power supply planning,placement,clock tree synthesis,routing,etc.,which is the focus of this paper.In the synthesis process,the DCT flow is used in combination with the problem of poor timing matching in the physical implementation process.In combination with the layout information in the physical implementation,the integrated timing convergence is accelerated,and at the same time,the power consumption is optimized and the clock gating is inserted during synthesis.In the physical implementation,a method based on data flow floorplan,insertion of physical units and a reasonable power supply planning strategy are given,among which the method of placing macros is highlighted.Using the hierarchical layout method,the placement design based on routing congestion and timing optimization is completed.The multi-source clock tree is designed to replace the traditional clock tree to converge the timing.The relationship between the number of clock source points in the module and the performance of the clock tree is analyzed.The clock propagation delay,clock tree skew,clock transition time,clock uncertainty,the issues of placement,cloning and merging of clock gating,clock tree levels and clock tree buffer types are introduced in the clock tree design.The theoretical analysis and corresponding solutions are given for the layout and routing congestion,crosstalk and power consumption problems encountered in the wiring process.In the DFM,redundant vias were used to replace the single via,and the filler and the metal fill were inserted to increase the manufacturing yield.In the static timing analysis,the mode and the sdc of the timing closure needed in this project are introduced.The advantages and disadvantages of the OCV,AOCV and POCV are compared.The static timing of the final P&R is performed.After analysising,the results are within the scope of repair.Left timing and physical rule problems are solved in the ECO process.The setup time is repaired mainly by modifying the cell size and replacing the cell threshold.The method of maintaining the time is mainly to increase the delay by inserting a buffer.The DRC repair is performed through a replacing of via,manual adjustment of jumpers,and adjustment of metal area are completed.In the end,strict DRC and LVS checks were performed using calibre,using Prime time to perform strict timing checks and the GDS can be taped out.The frequency of UMC_UCLK clock and SOCCLK clock reach 1.32 GHz,the total power consumption of this module is 103 mW,they achieved the anticipated goal.