Research On Cell-aware Based Efficient Testing And Test Cost Optimization

The continuous development of integrated circuit and the use of complex cells such as multiplexers and XOR gates in design have caused more and more untestable defects to be found in complex cells or even at the transistor level.The use of complex Fin FET threedimensional structures and IP reuse technology to speed up the So C design process also pose new challenges to testability testing.The traditional stuck-at fault model and transition fault model based on static and dynamic faults only consider the defects at the port of the library unit and interconnection lines between the units,and have gradually failed to meet the increasingly stringent zero-defect requirements of IC customers.New test methods like Ndetect,Gate-Exhaustive(GE)and Embedded-multi-detect(EMD)have introduce plenty of test vectors,not only leads to a significant increase in test cost,but also only increase the probability of detecting defects,which brought great limitations to the testing of actual products.To this end,the Cell-aware methodology based on cell layout modeling proposed by Mentor Company generated a user-defined fault model(UDFM)with defects in complex cells as the target defect,and tested chip manufacturing defects and improved chip yield.But this method has not been applied in actual chip testing.In response to this phenomenon,this study takes the IP core as an example,and introduces and implements cell-aware method-based fault modeling and test vector generation,simulation,and ATE testing in the project;then it is compared with the traditional fault model with comparative analysis of various aspects such as mechanism,the number of test vectors,test coverage,ATPG running time,etc.According to comparison results,compared to traditional fault models,the Cell-aware methodology can generate deeper into complex cells,and based on transistor-level modeling,generate a more comprehensive fault model to achieve more rigorous inspection of manufacturing defects to improve product yield;In addition,the low-speed and at-speed test vectors derived from the UDFM fault model based on the Cell-aware method,The number of covered defects has increased by 6.41 times and 5.94 times respectively;compared with the traditional method,the test coverage has increased by 1% on average,achieving a significant increase,indicating that this methodology has a significant effect on improving test quality.While improving the test quality,this methodology has also leads to an increase in the number of test vectors by 2-3 times and an increase in the running time of ATPG by nearly 1.5-2 times,which has increased the cost of testing.To this end,the project uses several way like suitable test vector generation method,comprehensive use of new and old fault model,the introduction of the Top_off process,and the combination of test vectors to optimize the pattern count.With the Top_off process,the project comprehensively utilizes the new Cellaware test vector and the test vector generated based on the traditional fault model.According to the test results,without affecting test coverage,the number of Cell-aware lowspeed test vectors was reduced by 4.1%,while at-speed test vectors achieved a 69.94% reduction in the number of test vectors at the cost of 5.99% test coverage;ordinary lowspeed and The high-speed test vectors decreased by 94.57% and 94.52% when the test coverage increased by 0.22% and 0.77% respectively;the results of these test vectors successfully passing the machine test also show that we have achieved the Cell-aware method in actual projects introduced and implemented and optimized its test vector generation reasonably to achieve efficient and reliable testing with as little testing cost as possible.