Research Of Test Patterns Generation Based On Boundary Scan Test Technology

Boundary scan test technology is being used widely in VLSI and correlative test area. Many overseas companies have designed advanced test apparatus and software for boundary scan. Up to now, internal research and application of boundary scan technology is still faintish corresponding to the one-up companies or countries, so there are many works to do in the future. With further application and development, boundary scan test can be carried out without professional apparatus, and be realized only in virtue of test software to test the chips or system with boundary scan units. In test software development, auto building of test patterns is a chief task, and also is the precondition for test control, test result analyse. Therefore it is critical work during the whole procedure, and it is studyed in details.As the foundation of test patterns building, in the article, the reason and foreground of useing boundary scan is mentioned firstly. Then, IEEE1149.1 standard is expatiated, such as test access port and test structure. Basic concept and interconnection trouble models are described in details, existing building arithmetics for boundary scan test are analysed. On the PCB designed with independence, detailed procedure of integrity test and interconnection test is provided in the article. Further more, according to current research state, test system consist of software and hardware design is brought up, and the principle is expounded.In section decribing auto building of test patterns, nettable and BSDL (Boundary Scan Decription Language) is describe in details. SVF (Serial Vector Format) which accords with international industry standard is used to describe test patterns. Walk " 1" arithmetic which has great trouble shooting ability is selected, at the same time, combining with boundary scan chain infomation of testing PCB, interconnectiong test patterns automatic generation is realized by program.At the end, PC program playSVF is achieved using code packet that is provided by xilinx. The program executes SVF test patterns file analyzing, and products boundary scan test pulse .Transferring the pulse via parallel port of PC, validating test on PCB is realized.