SOC Test Program Optimization For The High Efficiency

Marching into SoC era of integrated circuits development, the criticalcompete most depend on cost compete. How to develop the high efficienttest program becomes the most concerns of the testing industry.The cost of chips is made up with Wafer, Assembly, Testing. Testingis determined by test platform hourly rate, so it’s the most flexible processand easy to see the improvement results. Test time reduction can cause thewhole test cost reduction as well.This thesis is focusing on SOC test program optimization; the goal isto reduce test time. This solution based on existed test platform V93K,through the multi-approach of test program improvement to reduce theATE test time, At the meanwhile. Guarantee the results accuracy and keepmass production stability.The approach of test time reduction including, Test frequencyadjustment, Test method equivalent transition, Minor tuning of testhardware and test program optimization, Test result data collection andanalysis.On the condition of test stability, specific chosen appropriatemethod can help to optimize test program reasonable.Through above description of optimization test time, can help tospecific improve present test program. Then the test time can save around33%which lead cost down for the whole chip manufacturing, acceleratethe product launch cycle. Finally, this chip can keep the1stmarket shareconsistently.