Research On Chip Testing System Based On JTAG

The rapid development of electronic design technology not only drives the progress of the electronic manufacturing industry, but also puts forward higher requirements for the circuit board testing technology. On dealing with the circuit board of the high integration and high density, the traditional circuit board testing technology has been unable to meet the requirements. As a new type of testing technology, the boundary scan testing technology has been widely used in the electronic manufacturing industry.On the basis of deep research on boundary scan testing technology, this paper makes a further research on the algorithm of boundary scan testing vector generation, and analyzes the performance of various algorithms from two indexes of completeness and compactness, Combined with the traditional testing vector generation algorithm, a new algorithm for the optimization of complex networks is progressed. By analyzing the topology structure of the complex network, the complex network is divided into several sub networks according to the rules, and then the sub networks are tested for interconnection. This algorithm can overcome the shortcomings that the traditional testing vector generation algorithm cannot be applied to the complex networks; Then this paper puts forward a kind of boundary scan testing system design scheme, this scheme can perform the routine boundary scan test such as FPGA, CPLD, etc., which supports IEEE 1149.1 standard. Through the experiments, the scheme is proved to meet the design requirements in the index of the fault location and detection efficiency. Finally a simulation verification method based on coverage is proposed. In this method, the performance of the boundary scan test vector generation algorithm and test tool is realized by the process of the model establishment, the simulation of the fault and the comparison of the results and the result analysis.