The Study Of Design-for-Test Based On CCM3108

As the development of integrated circuits (IC), the density of chips becomes more and more complex. It is difficult to detect the defect in SOC with the traditional test technology. Therefore, IC design-for-test (DFT) technology is put forward to solve this problem. The main difficulty of DFT in SOC lies in the design of complexity, and a large number of sequential logics and the embedded memories. The sequential logics increase the difficulty of creating test patterns and extend the test time. The embedded memories which exist in the SOC chip will waste the port and increase the cost of production if we use the direct test method to detect them. Moreover the fault coverage of the chip production requirements must be greater than 95 percent. When the chip’s process is below 90 nm, it must be able to test the timing faults. The chip’s faults must also be detected when it integrated on PCB board. In order to deal with the problem mentioned above, the DFT circuits based on CCM3108 SOC chip which provided by Suzhou C*Core corporation has been designed.First, the full-scan structure has been designed for CCM3108 with the scanning test principle and some solutions which could make the fault coverage reach 97 percent have been proposed to detect the chip faults. And the clock gating structures, which decrease aboat 30 percent power, has been designed in this paper. Next the MBIST structure has been designed to test the faults of the embedded memories to save the number of chip’s I/O pins by modifiding March algorithm. In order to detect the timing faults, the at-speed scan test structure has been designed by using the PLL logics which exists in SOC chip. Then the boundary-scan logic has been designed to make sure the chip’s faults can be detected when chip integrated on PCB board. Finally, to save the test time, the deterministic logic BIST and adaptive scan test logics have been designed in this paper. The adaptive scan test logics can save more time and test cost and it does not affect the fault coverage although it increases about 0.11 percent of chip’s area. After the simulation and verification this chip design has been tapeout.The paper’s innovations include as follows:(1)The paper solved the problems which emerged in full-scan concrete and maked the fault coverage reach 97 percent. The adaptive scan test structure was designed to reduce the number of test patterns about 8.78 times and the test time for SOC was reduced aboat 6 times. And the chip’s area and power consumption were controlled within 10 percent. The test cost was reduced greatly in the SOC chip.(2)The march algorithm was improved in this paper and alternating inversion value of the address bit of the embedded memory which can cover more faults was used to improve the test efficiency.(3)The OCC controller structure was designed to save the equipment cost by using the high speed clock in PLL logic and low-speed clock in ATE.