Research And Design Of Millimeter Wave Frequency Synthesizer Applied To 5G Communication System

Millimeter wave is one of the attractive solutions that will make the future 5G communication system a reality,which makes millimeter wave chips become a hot research topic in recent years.As the core circuit of the RF front-end,the frequency synthesizer has a crucial impact on the quality of the 5G communication system.In the millimeter wave band,the continuous increase of the phase noise requirements of the system and the deterioration of the noise performance of the frequency synthesizer become inevitable This contradiction is particularly evident in millimeter wave RF receivers.This paper investigates the research status of the millimeter wave frequency synthesizer,analyzes the mainstream circuit structure of the millimeter wave frequency synthesizer,and then studies the frequency synthesizer based on the phase-locked loop structure from the module to the system,and completes it under MATLAB.System modeling and simulation determine the loop parameters of the phase-locked loop.Next,this paper designs each circuit module of the frequency synthesizer based on the phase-locked loop structure,including:A voltage controlled oscillator with ultra-low phase noise.The voltage-controlled oscillator uses a double negative resistance structure to provide current bias to the resonator from the top,avoiding the deterioration of phase noise caused by the line bias effect,while improving the symmetry of the waveform.The devices are all DNW type,which can effectively reduce Substrate coupling noise has also designed high-Q inductors and conducted electromagnetic simulations.After the final voltage-controlled oscillator simulation results,the tuning range can cover 24.75 GHz ~ 27.5GHz,and the phase noise in the entire tuning range is less than-103 d Bc / Hz @ 1MHz,-123 d Bc / Hz @ 10 MHz,the circuit uses both 2.7V and 1.2V Voltage supply,power consumption is about 10.0m W.A frequency discriminator based on RS trigger and charge pump with high precision.Among them,the frequency discriminator phase detector reduces the overlap of the differential switch control signal by adding a transmission gate,and eliminates the phase discrimination dead zone by adding a controllable delay module;the charge pump adopts a steering charge pump structure,and a complementary switch is designed to reduce the clock Feedthrough,the use of cascode structure and op amp clamping technology greatly improve the output impedance of the current source and reduce the current mismatch.The simulation results after combining the frequency discriminator and the charge pump show that the charge pump DC mismatch is less than 0.2 ‰,the current noise at 10 k Hz is about-222 d BA,the current noise at 100 k Hz is about-230 d BA,and the current noise at 1MHz is about-224 d BA.A low-power frequency divider that can achieve a frequency division ratio of 495 to 550,including 4/5 prescaler,16/17 prescaler,and two programmable counters.The 4/5 prescaler uses a CML structure.By analyzing the factors that restrict the speed of the CML latch,the parameters and circuit structure are optimized,the working frequency of the prescaler is increased,and the NAND gate is embedded in the latch.While reducing circuit power consumption,the working frequency of the prescaler is further increased.Except for the 4/5 prescaler in the 16/17 prescaler circuit,all are implemented with differential transmission gate registers,which greatly reduces the power consumption of the divider.Programmable counter A expands the critical path delay from one clock cycle to three clock cycles by adding an additional D flip-flop,and the operating frequency of the counter is more than doubled.Programmable counter B counts by using the falling edge of the clock.This method solves the problem that the counter cannot count 1.The post-simulation results of the frequency divider show that the frequency division range of the prescaler covers 24.75 GHz ~ 27.5GHz,and the noise of the prescaler is-152 d Bc / Hz @ 1MHz,-157 d Bc / Hz @ 10 MHz The dualmode frequency divider can achieve a frequency division ratio of 495 ~ 550,and the total power consumption is about 17.4m W.Finally,based on the SMIC 55 process,we independently completed the design of all circuits and layouts for frequency synthesis,including voltage-controlled oscillators,frequency and phase detectors,frequency dividers,charge pumps,loop filters and other circuit modules.It is 1.05 mm * 0.6mm.After post-simulation,the power consumption is about 33 m W,and the lock time is less than 4?s.After noise fitting,the final phase noise is about-103 d Bc / Hz @ 500 k Hz,-105.9d Bc/Hz@1MHz,-123 d Bc / Hz @ 10 MHz,It can meet the application of 5G communication system.