Analysis And Design Of Frequency Synthesizer Of Digital Broadcasting Receiver Front-end Based On Deep Submicron CMOS Technology

The digital technology in radio and communications, especially the distribution and transmission, is the global trend. There are several digital standards, such as DRM (Digital Radio Mondiale) and DAB (Digital Audio Broadcasting), In this dissertation, a frequency synthesizer applied for a DRM/DAB receiver is studied and analyzed. Based on the SMIC’s 0.18-μm RF-CMOS technology, a PLL-based frequency synthesizer has been designed and fabricated for the digital radio receiver. Finally, the receiver’s feature and function is also verified by a system application.In this thesis, the main architectures of the frequency synthesizer have been studied and analyzed. Referring to the specification of the digital radio receiver, an integer-N charge pump PLL-based architecture has been chosen. The parameters and specifications of various modules have been set and optimized, and some behavioral level simulations have been employed.A wide band LC-VCO (LC-tuned voltage controlling oscillator) is designed in the thesis. Based on the LTI model and LPVT model of the phase noise, the principle and optimization techniques have been discussed. A drain-resistor-inserting method has been presented to reduce the in-band phase noise, and some quantitative analysis has been put forward. Referring to the covering band of the PLL, the relationship between the inductor and capacitors has been calculated and simulated, and the parameters of the passive devices have been optimized. An auto frequency calibration (AFC) module has been designed for the proposed VCO.The chip is fabricated in a SMIC’s 0.18-μm RF-CMOS process and used with wire bonding technology on PCB test. The measured results of the proposed VCO meet the requirements and achieve a good performance in phase noise characteristic. The AFC module has accomplished the calibration function during the test as well.A feedback divider of the PLL has been proposed. Referring to the specification of the digital radio receiver, the division of the feedback divider is relatively large and the dividing range is wide. A CML dual-mode divider has been designed for the proposed LC-VCO. The noise and jitter characteristic of the divider have been discussed and analyzed. A glitch-suppressed DFF has been used in the proposed PS counter. The chip is fabricated in the same SMIC’s 0.18-μm RF-CMOS process as above and used with wire bonding technology on PCB test. The measured results show that the feedback divider has accomplished its function during the VCO oscillating range.A phase frequency detector (PFD) and charge pump (CP) have been designed. A dead-zone-free PFD architecture has been used in the designed PLL. The control signals of the CP are differential. A charge pump consisting of dual error amplifiers has been proposed, and the mismatch performance has been optimized. The reference spur due to the non-ideal characteristic of the CP has been discussed and analyzed. The chip is fabricated in the same SMIC 0.18-μm RF-CMOS process as above and used with wire bonding technology on PCB test. The measured results show that the PFD has accomplished its correct logic function and a good mismatch performance of the charge pump is achieved.An orthogonal frequency divider has been designed. Based on the theory of the harmonic mixing and harmonic suppression, an output divider has been proposed to generated quadrature LO-signals. In the low frequency band, the LO-signals of the digital receiver are 8 ways of pseudo-sinusoidal signals applied with harmonic rejection mixer. In L-band, the LO-signals of the digital receiver are normal quadrature signals with 25% duty cycle to enhance the conversion gain of the mixer. The chip is fabricated in the same SMIC’s 0.18-μm RF-CMOS process as above and used with wire bonding technology on PCB test. The measured results show that the divider has accomplished its correct logic function and the rejection of the unwanted harmonics is improved.All the designed modules are finally integrated in one PLL chip, and the chip has accomplished its correct function. The PLL is also integrated onto the same ship with the receiver and register modules, and a transceive system is set under the laboratory environment. The related measured results are given, and a transmitting and receiving test in the lab is completed.