Research And Implementation Of Key Techniques In 3D Clock Tree Synthesis For Noise Avoidance

Since the IC industry has a quite rapid development in recent decades,the IC devices gradually reaches its physical limits.Many experts work in both academia and industry hold the view that the 3D IC technique based on TSV(Through-Silicon Via)technique may lead the change of the semiconductor technology.In the 3D clock network,the clock signal can spread not only in the horizontal directions but also the vertical direction.And TSVs may also impact clock network due to their own parasitic effects.In order to build a cost-efficient 3D clock tree,the thesis will extend the traditional clock tree synthesis algorithms into 3D area.The proposed3 D clock tree synthesis includes abstract tree topology generation,layer embedding,routing and buffering.The thesis also builds the model of the crosstalk nosie between two neighbor TSVs and present the method of noise avoidance.Accoding to the method of TSV-noise avoidance,an algorithm which can guarantee the minium TSV insertions is proposed.And a clock tree topology optimization algorithm is also proposed for recountsructing some specific subtrees.The simulation results show that the total wirelength and TSV density are optimized.In the other hand,the thesis also builds an optimized 3D clock tree synthesis flow according to the TSV density and crosstalk nosie.Experimental results show that the clock delay performance can be increased by up to 57.14% and TSV usage can reduced by up to 90.7% in expense of wirelength increased by 1.03% to 25.14%.