Low Power Physical Design And Clock Tree Synthesis Of A Motor Control Chip

With the rapid development of integrated circuit design and manufacturing technology,low power consumption of chip has become a very important issue in design.Based on the physical design of an on-board motor control chip,this paper studies the low-power implementation method in the key phase of physical design.Based on SMIC 0.18 um technology,a low-power clock tree synthesis method is realized.Based on this method,the physical design of the whole chip is completed.Firstly,this paper investigates the development status of low power chip design at home and abroad,then discusses the types and sources of power consumption in digital integrated circuits,and summarizes the basic ideas and theoretical methods of reducing dynamic and static power consumption.Various advanced technologies with low power consumption under existing deep sub-micron meter processes are described.According to the actual situation of the project,the idea of dynamic power optimization for clock tree synthesis is determined to reduce the power consumption of digital part of the chip.In the floor planning stage,the voltage drop is optimized locally to reduce the voltage loss.The physical realization and power simulation are carried out to verify the parameters of the clock tree synthesis stage,including clock latency delay,transition time,std-cell fan-out,the influence of the selection of integrated units on the power and timing of the clock tree,and the order and characteristics of the clock tree synthesis.In order to reduce the dynamic power consumption in the clock tree synthesis,the basic method of synthesizing the main clock first and using large driver unit at the root node is summarized and put forward.This paper designs and implements a low-power physical layout design of motor control chip based on SMIC 0.18 um CMOS technology.The physical layout of the chip covers a total area of 4000 um x 3000 um.After power simulation,the results show that in the process of clock tree synthesis,all parameters have a certain impact on power consumption,and the power optimization of the digital part reaches 36%,After the chip is tested normally,it shows that the design is in line with expectations.