| The design and VLSI implementation of CMOS decimation and interpolation half-band filters, targeted for use as rate converter modules in the design of digital mobile radio transceivers, are presented in this thesis. Two designs have been proposed with performance and characteristics evaluated through simulation and functional verification. The first design is of a dedicated integer fixed coefficient 27-tap decimate and interpolate-by-two half-band FIR digital filter, the design method based on Parks-McClellan algorithm yields power-of-two coefficients, thus reducing the filter hardware complexity and power consumption. The second design is of a programmable 7-tap decimate and interpolate-by-two half-band FIR digital filter. The impulse response of the programmable filter is user-selectable and can be generated using various half-band filter design techniques. The choice of polyphase filter architecture made a single-chip design feasible for implementing both decimation and interpolation half-band filters. Simulation results based on MOSIS 1.2... |
