The Research And Design Of 512 Times Digital Decimation Filter In Sigma-Delta ADC

ADC is the core module of integrated chip. In recent years, the researches in Sigma-Delta ADC have been more in-depth, also its applications are also becoming more widespread. Digital decimation filter is an important module of Sigma-Delta ADC, which directly determines the area and power consumption of the overall design, so choose the appropriate digital filter structure has great significance for the whole ADC design.First, we briefly introduce the basic principle of Sigma-Delta ADC, and establish a MATLAB model for Sigma-Delta modulator. Then we have focused on the analysis of the principles and structure of the CIC filter, FIR compensation filter and HB filter, and design and optimization for them according to the corresponding parameters by MATLAB,finally determine the structure, the design idea and the design method of the filter. This paper design and implement a digital sampling filter with sampling rate of 512, it adopts the multistage structure with the cascade integral comb filter, the compensation of FIR filter and half band filter, their extraction ratio were 128,2,2,respectively. However the passband frequency attenuation of CIC is big, so we need design a FIR compensation filter to effectively compensate the attenuation of CIC filter. In order to reduce the operation complexity of filter, we have relized CSD encoder for the coefficients of compensation filter and half-band filter. Use the single bit pulse output signal of one order sigma-delta modulator as test vectors, then using Simulink in MATLAB to simulation. To realize FFT analysis for the output data and make sure that it can meet our performance requirements.By writing Verilog language and transferred to the test code generated by the MATLAB to finish the comprehensive validation of the filter, including hardware circuit design and function simulation.Sigma-Delta ADC output effective resolution is 11.66 bit, after three digital sampling filters, the output resolution is 11.51 bit, so it meet the design requirements.