Research On Digital Intermediate Frequency Processing Techniques Of Software Defined Radio Transceiver For Industry Private Network Applications

Industry private network is a major communication network for national security, military, finance, energy, government, industryand other important sectors. It is related to people’s livelihood problems. The purpose of this project is to design a wireless broadband radio frequency chipsto meet the needs of different industries private network. Thebandwidth and frequency of the chip are configurable. This thesis mainly researches the chip design, simulation, implementation and testing processof the digitalintermediatefrequency(IF).Due to a wide variety of industry private network, the chip was designed usingsoftwaredefined radio(SDR) technologyin order to cover as much of the private network applications.Softwaredefined radiohas a large advantage in supporting multiple bandwidth and frequency because software is flexible and configurable. The design belongs to a transceiverchip which is based on digital intermediate frequency structure of softwaredefined radio.Digital IF includes digital upconversion and digital downconversion. Digital upconversion is a process of interpolation and mixing for baseband signal. Digital down conversion is a process of decimation and mixing for IF signal. Since both interpolation and decimation need filters, this design mainly uses halfband filter and cascade integrator comb(CIC) filter. They are faster and take up less space.According to the different application bandwidth, industry private network can be divided into narrowband network and broadband network. Depending on whether mixer is needed, narrowband network can be divided into internal demodulation andexternal demodulation. Thedigital upconversion and digital downconversion each has 15 modes. The maximum sampling rate is 322.56 MHz. Bandwidth ranging from5 k Hzto 20 MHz can be configured. 2MHz low IF modulation and demodulation are supported. Numerically controlled oscillator(NCO) which does not produce spurious is used in up-conversion mixer and down-conversion mixer. Filters are reused in different operating modes and it can reduce the size and area of the entire digital design.According to design specifications, the thesis set out the parameters of each module firstly.Thenthe circuit is implementedusing Verilog hardware language. The function and performance are verified by Modelsim simulation. Then we use the back-end tool to complete the digital synthesis and layout. The chip taped out after post-route verification. The area is 3.2mm2. There are total of 480,000 standard unit. The maximum power consumption is 33 m W. The chip has good test performance. All bandwidth meet the design requirements. The digital upconverter band rejection is around55 d B. The digital down converter band rejection is around60 d B. The output signal SNR is above 52 d B. The receive sensitivity of the whole system can reach-110 d Bm with a 10-3 bit error rate and it meet project requirements.