| As a link between analog and digital circuits, ADC play a crucial role in the on-chip system. In addition to the static and dynamic index, area and power consumption has become a primary concern in the design. Because Sigma-Delta modulator using the oversampling and noise shaping technology, so the Sigma-Delta ADC easy at a lower cost to achieve high accuracy, and sufficient to meet the requirements of the audio signal frequency, audio frequency signal, it has been widely used for digital audio system.Digital decimation filter as an important component of the Sigma- Delta ADC,largely determines the Sigma Delta ADC's area and power consumption. Digital decimation filter cascaded by CIC filter, FIR compensation filter and half-band decimation filter. The higher the sampling frequency of the CIC filter lead to larger power consumption The structure of CIC filter is improved to reduce the power consumption and the chip area is reduced. AS half-band decimation filter and FIR compensation filter having a multi-stage filter coefficients, so that requires a lot of memory to store the filter coefficients, increase the use of the area. The coefficient of the filter using the CSD encoding technology, reduces the computation and complexity, reduce the chip area.The digital decimation filter achieve 512 times decimation. The CIC decimation filter adopts five cascade structure, it can complete 64 times extraction. FIR compensation filter complete 2 times extraction. The first and the second half band filters were completed 2 times of extraction. After comparative analysis, choose recursive structure to achieve CIC filters,using the method of ripple approximation to design FIR ripple compensation filter and half band filter.This paper design a digital decimation filter. The input sampling frequency and output sampling frequency is respectively 1024 kHz and 2 kHz, its input and output bit width are 5 bits and 18 bits, can achieve 512 times extraction, and the output bit width is 18 bits. |
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