Design Of Digital Module In 24-bit Sigma-Delta ADC

With the increasing development of electronic technology,digital signal processing technology has become more and more mature,and there is an increasing demand for related technologies in the fields of electronic medicine,smart home,and industrial control.The analog-to-digital converter ADC,as a conversion circuit between analog circuits and digital circuits,is an important module for many electronic products.The Sigma-Delta ADC based on oversampling technology and noise shaping technology has the advantages of high accuracy,high signal-to-noise ratio and easy integration,so it has been widely used.SigmaDelta ADC is composed of modulator and digital decimation filter.The digital decimation filter circuit determines the power consumption and area of the entire ADC system.How to use a reasonable digital filter structure and cooperate with related control circuits to effectively reduce the area and power consumption of the Sigma-Delta ADC system is of profound significance.This paper designs a digital filter module in the 24-bit Sigma-Delta ADC used in the electronic medical field.The digital module mainly includes a register control module,a clock and reset module,a decimation filter module,and a mode conversion and data trimming module.The registers in the register control module can be read and written offchip to realize the configuration of related parameters and data Storage.Among them,the digital decimation filter module adopts a three-stage cascade filter structure,the first stage is a CIC filter,and its decimation factor can be configured as 32,64,128,256,512;the second stage is a compensation filter,stop-band The attenuation is 90 d B to realize the compensation of the passband of the CIC filter and complete the decimation by 2 times;the third stage is a half-band filter,adjust the filter stopband attenuation to 100 d B,and complete the decimation by 2 times.In Simulink of MATLAB,the model building and simulation of various levels of filters were carried out.The results showed that the passband ripple of the filter was less than 0.001,and the stopband attenuation was less than-100 d B.In the RTL design of the filter,the compensation filter and the half-band filter both use the principle of Noble identity,polyphase decomposition technology and coefficient symmetry to optimize the circuit structure.The coefficients are quantized by 20 bits and then coded using CSD and shifted.Adding instead of the multiplier effectively reduces the power consumption and area of the decimation filter module.The filter module and other modules are simulated and verified by EDA software,and the function of configurable extraction factor is realized.When the total decimation factor changes from 128 to 2048,the signal output rate changes from 2064 Hz to 163 Hz,the effective number of bits ENOB increases from 17.23 bits to 19.24 bits,and the signal-tonoise distortion ratio SNDR increases from 105.5 d B to 117.7 d B.Under the SIMC 0.13?m process,the Design Compiler is used to logically synthesize the design,and the circuit layout is completed in the IC Compiler to obtain the layout of the digital module in the Sigma-Delta ADC.