The Design And Research Of Sigma-Delta Modulator And Decimation Filter

With the continued advances in digital technology, ADC is widely used in every aspects of electronic technology. There is a now very popular ADC called Sigma-Delta ADC which is low-speed and high-precision. It is mainly used in processing an audio signal.The Sigma-Delta ADC is mainly made of a modulation section and a low-pass decimation filter section. It mainly uses over-sampling technology, noise-shaping technology and digital-filtering technology. Over-sampling and noise-shaping technology can push most of the quantization noise to the high-frequency range. Then use a low-pass filter to filter out high-frequency noise. Thereby the SNR and the precision in signal band can be improved.After we discussed the basic principle, structure and achieve methods of different types of Sigma-Delta ADC in detail, we proposed an overall design scheme. The parameter structure is set as follows: 2-1MASH modulation, 1bit quantization, OSR=128, resolution 16 bits. The input signal is a 44 KHz sinusoidal signal. The sampling frequency is 5.632 MHz. Build overall system structure under SIMULINK, determine the coefficient factor specific circuit, then simulate in the system level, the intended target can be reached. At last, analysis and computational modeling through Sigma-Delta toolbox for non-ideal factors circuits,then figured out the specific values of non-ideal factors that can make good modulation effect.Then we research digital decimation filter, after analysis the principle of decimation, we propose a multi-stage decimation of implementation structure. We focus on two types of high property, widely-used special FIR filter: Cascaded integrator comb filter and Half-band filter. We researched their principles, properties, structure, advantages and so on.We proposed a multi-stage structure of 128 times decimation filter program. The frequency of input signal is 5.632 MHz. After decimation, the frequency of output signal is 44 KHz. The passband rippee should be less than 0.01. First we set all kinds of parameter of CIC filter and half-band filter, including structure, order, multiple of decimation. And we proposed a CIC compensation filter according to the characteristics of CIC filter. We do the modeling and simulation in MATLAB, verified the rationality of the structure. Then we generate Verilog HDL, simulate the decimation multiple in ModelSim.From the simulation results, the designed ADC can achieve design goals of 102 dB SNR and 16 bits precision. Digital decimation filter's input frequency 5.632 MHz, output frequency 44 KHz, pass-band frequency 20 KHz, 128 times of decimation.