The Design And Verification Of Decimation Filter For ∑△ADC

With the rapid development of IC technology and digital signal processing, high-resolution A/D converters are required to be integrated in the same substrate as digital signal processor does. The highest resolution achieved by conventional Nyquist rate A/D converters are limited by the matching precision of components, so it is impossible to achieve high resolution with this kind of A/D converters in a standard VLSI CMOS technology unless a special technology is applied.Sigma Delta modulators, combined with oversampling, effectively attenuate the in-band quantization noise in the output signal and enhance the signal-to-noise ratio(SNR) through the shaping of the quantization error, thus they make it possible to do high-resolution converting using coarse converters. Compared with their Nyquist rate counterparts, oversampling Sigma Delta A/D converters, taking the advantage of state-of-the-art VLSI technology featured increasing scale and speed, transfer the pressure of high resolution to digital system and greatly release the requirement on the performance of analog circuit. A sigma-delta A/D converter consists of a sigma-delta modulator and a decimation filter, especially the area and dissipation of the chip are greatly cost in decimation filter.The decimation filter for the Sigma Delta ADC is implemented in this project, whose resolution is 24, ouput frequency is 44.1 kHz, pass band ripple coefficient is 0.02dB, and stop band attenuation is 80dB. This dissertation gives some description about the basic principle and structure of the sigma delta modulator, and emphatically focuses on the method of the design and circuit implementation for the decimation filter, such as the determination of the decimation rate, the number of the order and the delay coefficient for the CIC filter; the chose of the complementary and the interpolated coefficient for the Interpolated Second-Order Polynomials, as well as the design of the FIR filter, the Half-Band filter, the Booth and the CSD multiplier. Additionally, this paper presents two methods to reduce the area of the die, the first method is the utilization of the fifo whose depth is two, and the other is the time-division multiplexing technique of multiplier. To reduce the power dissipation of the chip, the gated clock technique is introduced. At last, in order to verify the function of the design, a suitable verification method is presented.uring the design of the filter, Matlab is used to choose the optimal parameters, and the circuit is implemented in Verilog HDL, simulated to verify the function with Modelsim. Finally based on the UMC 0.18um technology library, the Verilog codes are synthesized to gates and the static timing analysis is dealed with the help of the Design Compiler and Primetime.