| The architecture of an FPGA has a significant effect on area and delay. In deep-submicron designs, the interconnect resistance and capacitance accounts for the majority of the circuit delay. In the first part of this thesis, we perform a detailed study of the FPGA logic block architecture to determine the impact of logic block functionality on performance and density. In particular, in the context of lookup table (LUT), cluster-based island style FPGAs we look at the effect of LUT size and cluster size (number of LUTs per cluster) on the speed and logic density of an FPGA. The second part of this thesis explores the area and delay properties of a hardwired logic block architecture. This involves a new packing algorithm. |
