Look-up Table Model Of Gate-All-Around Reconfigurable Field Effect Transistor And Logic Gate Circuits

With the rapid development of semiconductor technology,it has become more and more difficult to break through the limitations of physical size.Gates around nanowire have become the core device structure for technology nodes below 5nm.The reconfigurable field-effect transistor device(RFET)benefits from its own structural characteristics,through the polar gate(Program gate,PG)control the type of carriers flowing through the channel.The transistor can achieve dynamic reconfiguration between N-type and P-type conductivity,which broadens the functions of traditional transistors.In this way,through the reconfigurable characteristics of RFETs,it is possible to use a smaller number of transistors to achieve richer logic outputs which has broad application prospects.The main research contents and results of this paper are as follows:Firstly,the structure of RFET is built by TCAD tool.Under different nanowire diameter,different nanowire length,different isolations and different temperature,the DC characteristics of RFET are simulated and analyzed.Under different drain bias,the parasitic capacitance of the device is studied.Secondly,under different V_ds conditions,I_ds-V_cgs,C_cgs-V_cgs,C_cgd-V_cgs,C_pgs-V_cgs,C_pgd-V_cgs,C_cgpg-V_cgscurves of different sizes and different V_pgsare simulated by TCAD,which form look-up tables respectively.And through the Verilog-A language,the look-up table models with fixed polarity gate voltage and variable polarity gate voltage were constructed respectively.The built-up look-up table model is used to simulate the I-V and C-V curves of the device and compared with the TCAD simulation curve to verify the accuracy of the constructed model.Finally,based on the RFET look-up table model constructed above,the most basic inverter is simulated,and the results show that it has the best balance of power consumption and delay when the power supply voltage is 2V_th;then,a strobe signal select is built to control the logic output of NAND/NOR,AND/OR,XNOR/XOR,OAI/AOI circuits.According to different input conditions,the propagation delay,average power consumption,and PDP are simulated.The results show that when the input signal of the NAND gate circuit is a falling edge,the delay is the lowest.And when the input signal of the NOR gate circuit is a rising edge,the delay is the lowest;the OR gate is contrary;XNOR and XOR have the lowest delay when in2 is falling;for OAI and AOI gates,the delay when the output is falling is lower than the rising case.However,the power consumption of OAI gate is more affected by the change of input than that of AOI gate.Besides,we explored the six-tube static memory circuit of RFET under the power supply voltage of 1.0V,and its read or write speed and read or write stability are evaluated.