Design Of A Configurable Logic Block Based On FPGA

With the increasing mask of application specific integrated circuit(ASIC)and the risks that must be borne by the market if design errors occur,field programmable gate array(FPGA)devices with repeatable programming capability have been more and more widely used in many fields such as communication,industry,data processing and so on.Programmable Logic Block(CLB)is the core configurable logic unit in FPGA.The logic function of FPGA is realized through the configuration of CLB units and large-scale cascade of CLB units.This paper mainly aims at CLB units in FPGA to find a high-performance CLB implementation method,using 28 nm complementary metal oxide semiconductor(CMOS)technology from Global Foundry.In this paper,a fully customized design method is adopted.Firstly,the implementation structure of each component module in the CLB structure is studied,and a CLB implementation structure with complete functions and saving circuit resources is proposed.Then,the detailed circuit design of each module is carried out for CLB,and various types of logic functions are simulated to ensure that the CLB unit realized in this design can realize complete combination and timing logic functions,such as ROM function,RAM function,shift register function,multiplexer function,etc.Finally,the layout design of CLB circuit is completed.Based on the design ideas of FPGA products at home and abroad,this paper focuses on the development trend of CLB structure and the main factors that determine its circuit functions and characteristics,reasonably divides CLB cells,adopts the optimal composition structure that can be realized under the current domestic technical background,and optimizes each composition structure respectively in order to obtain better circuit characteristics.For example,a simplified structure of programmable registers is proposed,which greatly saves circuit area while ensuring basic sequential logic capability and lower path delay.After simulation and layout design,the CLB units designed in this paper can realize various types of logic functions,which lays a foundation for further building FPGA chips designed by the project to have efficient,complex and diverse logic functions.