| Due to the advantages of stable performance,high confidentiality,high reliability,and strong radiation resistance,Anti-fuse Field Programmable Gate Arrays(FPGA)has been widely used in aerospace,special industry,and other fields.Based on the metal oxide semiconductor(MOS)transistor gate oxide structure,Anti-fuse FPGA does not rely on expensive and scarce dedicated anti-fuse process,and has become a research hotspot in recent years.In this thesis,the programming architecture of antifuse FPGA based on complementary metal oxide semiconductor(CMOS)logic technology is investigated,and the chip layout,test verification,industrial implementation on 0.18 um CMOS logic process are conducted.The main research contents include:(1)A complementary matching dual MOS anti-fuse(CMDA)configuration storage unit structure is proposed,and Completed the optimization and testing of programming process parameters.By modeling the breakdown of equivalent circuit of MOS gate oxide,four configuration storage unit were designed,including CMDA,modified triple transistors single anti-fuse(MTTSA),recirculating triple transistors single anti-fuse(RTTSA)and cross structure dual anti-fuse(CSDA)configuration storage unit.Through chip test,multi-factor test verification and statistical analysis,the optimal configuration storage unit are obtained.The influence of programming process parameters such as programming voltage,programming time step and programming frequency on programming performance has been revealed,and the programming process parameters optimization is conducted.Finally,the output voltage amplitude matching optimization,complementary matching storage optimization,and high-voltage programming power optimization are analyzed for the CMDA configuration storage unit.Results show that the average programming time of the CMDA configuration storage unit is about 25 ms,the success rate of programming is higher than 84%,which is high with good consistency,compared with existing research results,it has advantages in amplitude of output voltage,capacity of resisting disturbance,and complexity of programming control.(2)A four-quadrant parallel programming method of anti-fuse FPGA is proposed.The impact of key factors such as the number of IO pins,programming current,programming power supply oscillation recovery time,and design complexity on the parallel programming area are explored,and established a four quadrant parallel programming scheme,design the programming architecture of complementary matching dual MOS anti-fuse FPGA,and the design of programming circuits,addressing structures,programming download software and programming downloader are completed.Through a large number of programming tests,when the resource usage rate reaches 50% and 70%,the programming time base on four-quadrant parallel programming method is only 62.03% and 38.99% of similar-sized FPGA abroad respectively,indicating the effectiveness of the proposed four-quadrant parallel programming method and overall programming architecture.(3)A systematic testing method for MOS type anti-fuse FPGA has been designed,and completed the testing engineering implementation.Introduced the design and implementation of complementary matching dual MOS anti-fuse FPGA chip,complete chip layout design and chip manufacturing 。 At the same time,complete the design of development software of complementary matching dual MOS anti-fuse FPGA chip.A systematic testing method for MOS type anti-fuse FPGA chips is designed,and key testing steps such as programmability testing,functional testing,AC parameter testing,and production testing are detailed in this testing method.Based on this systematic testing method,the design testing and production testing of complementary matching dual MOS anti-fuse FPGA chips are completed.The qualified chips have passed the user’s overall system application testing and are eligible for large-scale production,this indicates the effectiveness and reliability of the systematic testing method. |
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