Improving FPGA designs with incremental logic resynthesis and shortcut-based routing architecture

Field Programmable Gate Array (FPGA) has a dominating market in digital system prototyping and reconfigurable computing. To make a flexible and efficient FPGA chip both the hardware architecture and the design tool should be further engineered. An innovative architecture always requires excellent development of EDA tools to fully explore the intrinsic merits of the hardware.;FPGA Technology Mapping is an important design automation problem which affects placement and routing dramatically. Depth-optimal technology mapping algorithms were proposed and produced quality mapping solution for delay minimization. However such algorithms have not yet considered to further reduce area consumption using the powerful logic transformation techniques.;On software side, we propose a versatile approach to combine logic transformation and technology mapping. In addition to a level-reduction scheme, we also present a method of reducing the number of LUTs used while keeping the depth optimality. Our approach is based on a greedy but effective heuristic to choose good alternative wires for transformation. Large number of experiments were conducted to analyze the effectiveness of the system. Our results show that our approach can effectively reduce at least 5% (up to 25%) of the area over initial mapping by various state-of-the-art FPGA technology mappers. Furthermore, we found that the delay performance can be improved by 5% when the area is reduced by our system.;On hardware side, we present a study on the effect of direct and fast routing hard-wires in FPGA routing architecture. Based on the routing pattern analyzed from real routing data, we proposed a so-called shortcut -based routing to handle short and localized routing requirements. Experimental results show that the shortcuts are well utilized and it allows a better average wirelength usage in the whole routing architecture.