A Custom Design Of Configurable Logic Block For FPGA

Configurable logic blocks is the core of the FPGAs which makes FPGA be able to achieve a variety of digital circuit structures.The quality of the block's design directly effects the performance of the FPGA and the maximum system gates that FPGA included. Therefore,the design of the configuration logic block is the most important thing in the design of FPGA devices.The goal of this paper is to develop a method of designing a configurable logic block , and design a configurable logic block with 130nm CMOS process which can be used to construct a 10 million system gates FPGA device.At first, the overall structure of the configurable logic block is designed by combining the experiment method and CAD tool with the top-down approach. Secondly, each module of the block is implemented regarding to their specific functionalities. Third, the speed optimization and determination of the transistor sizes are carried out using Elmore linear model and logic effort method. Finally, the overlook of the layout is drawn by the structure and the area. In the end after evaluating the power consumtion of the block we verified the functionality and performance of the block through simulations .The completed configurable logic block has a unique fast output path of the lookup table. Thus, it is 10% faster than Xilinx VirtexII when it is used indepently.The configurable logic block also has a fast carrychain increasing the performance of the adder and the configurable store unite is able to be set as a synchronous / asynchronous latch / D flip-flop, which increases the volatility of the memory cell. Moreover, by introducing the low-power process, this design reduces the static current to 441.46nA, which leads to a significant reduction to the whole static power of the FPGA device.The design can be used to construct a 10 million system gates FPGA and the function of the look-up table, programmable memory, carry chain and other modules are verified by the MPW tape.