FPGA-based MPEG-4 video encoder SOPC design with performance acceleration of motion estimation block

Multimedia-embedded applications, have become an integral part of our lives. They are also used in fields like medicine and security which demand quality and reliability. Compression plays a key role as a good compression should supply easy storage and transmission without loss of information. MPEG-4 is a widely used ISO/IEC standard. MPEG-4 builds on the proven success in the fields of digital television, interactive graphics applications and interactive multimedia.;The goal of this thesis was to design and implement a hardware accelerator for the motion estimation part of the MPEG-4 encoder using FPGA (Field Programmable Gate Array) as the design technology. To achieve this goal, multiple steps were performed. First, for comparisons reason, the MPEG-4 encoder was implemented in software in an earlier version of the design. The Nios-II soft processor was used to develop the system-on-a-chip (SoC) model. The Altera Quartus II software was used as the simulation and synthesis tool. Second, an analysis of the execution timings for the different modules of the MPEG-4 encoder was performed. Analysis results revealed that the motion estimation module was the most time-consuming block and consumes 20% of the total execution time of the encoding process. Third, in order to accelerate the MPEG-4 encoder, the motion estimation block was selected for the hardware implementation, and a hardware accelerator was designed and verified. Finally, performance metrics of both modules were measured and evaluated.;Performance measures revealed that the motion estimation block when implemented in software only yields an execution time of 17.95 ms (run on Altera Cyclone-II FPGA chip). With the addition of the designed hardware accelerator, the hybrid hardware/software system (on the same FPGA chip), the same is performed in 0.031ms, thus giving a 563 times faster implementation. The time for executing the complete encoding for the given test bench was 101.14ms in software producing throughput of 312.8 Mb/s.;After embedding the motion estimation module developed in hardware, the same test bench takes 83.724 ms for complete encoding. The extra cost for the accelerator was calculated. The percentage utilization of logic elements increased from 11% to 24% (of the Cyclone-II FPGA chip resources). As the number of logic elements increased from 3513 to 8214, one can estimate that the designed accelerator utilized about 4700 FPGA logic elements. Even though it can operate faster, the output throughput was increased to 377.8 Mb/s. This 20% increase of throughput was achieved with the cost of the 4700 more logic elements of the FPGA. However, this increased throughput will need less time to operate, and hence can preserve energy consumption, and elongate the battery life of the video device.