| This thesis presents a pipelined analog-to-digital converter (ADC) employing a capacitor error-averaging technique with look-ahead decision and digital error correction concepts that has been implemented in a CMOS technology to achieve high linearity and high speed. The capacitor error-averaging technique can perform an accurate multiply-by-two (×2) function required in high-resolution pipelined ADCs, while a high gain op-amp has been designed to minimize error due to finite DC gain. Three clock phases are required by the capacitor error-averaging technique (rather than the conventional two clock phases), and the look-ahead decision technique takes advantage of this by allowing the residue amplifiers a full clock phase of settling time (rather than a partial clock phase in a conventional pipelined ADC). The fully differential pipelined ADC achieves a throughput rate of 20 Msamples/s and a linearity of 14 b without any type of trimming or calibration. The prototype ADC, fabricated in a double-poly triple-metal 0.5-μm CMOS process, exhibits a differential nonlinearity (DNL) of +0.23/−0.28 least significant bit (LSB), an integral nonlinearity (INL) of +0.95/−1.06 LSB, a spurious-free dynamic range (SFDR) of 91.6 dB, and a signal-to-noise ratio (SNR) of 74.2 dB with a 1-MHz input and a 20-MHz clock. The chip occupies an active area of 10.8 mm 2 including digital logic, output buffers, and bond pads, and consumes 720 mW at 5 V. |
