Design Of Pipelined SAR ADC For Space Applications

Human exploration for space has never stopped.A variety of sensors are used in satellites to obtain physical information of the outside world.The sensor readout system is responsible for amplifying,shaping and digitizing the weak electrical signals from the sensors.In the sensor readout system,analog to digital converter?ADC?is responsible for digitizing the analog electrical signal.The ADC is required to have the characteristics of high resolution,small area,low power and anti-radiation.In this dissertation,the Pipelined SAR ADCs aimed at the sensor readout system are studied and implemented.The main research works are summarized as follows:1.Digital correction and calibration techniques of Pipelined SAR ADCAimed at the analog front-end microelectronic system,a 10 bit 1 MS/s Pipelined SAR ADC prototype chip was designed and implemented in CSMC 0.35?m process.The chip adopts a three-stage structure with a resolution of 4 bit per stage,of which 1 bit is redundant.In order to improve the accuracy of the ADC,additive digital correction technique and weight-based digital calibration technique are used.The test results show that the differential non-linearity?DNL?of the chip is-0.47 LSB⁰.52 LSB,the integral nonlinearity?INL?is-1.08LSB¹.67 LSB,the effective number of bits?ENOB?is 8.9 bit and the power consumption is8.2 mW.2.Research and design of high-linearity Pipelined SAR ADCAimed at the digital front-end microelectronic system,a 12 bit 10 MS/s Pipelined SAR ADC prototype chip was designed and implemented in TSMC 0.18?m process.The chip adopts a two-stage structure.The resolution of the first stage is 6 bit.The resolution of the second stage is 8 bit.In order to improve the linearity of the ADC,a V_cm-based stage circuit and a consistent routing strategy for DAC capacitor array are used.The test results show that the DNL of the chip is-0.57 LSB¹.06 LSB,the INL is-1.54 LSB¹.38 LSB,the ENOB is 10.8 bit and the power consumption is 10 mW.3.Research and design of low-power Pipelined SAR ADCAimed at mixed Signal micro control unit system on chip?MCU SOC?,a 12 bit 2 MS/s Pipelined SAR ADC chip was designed and implemented in TSMC 0.18?m process.The chip is integrated into the MCU SOC.In order to reduce the power consumption of the ADC,the unit bridge capacitor SAR ADC is employed in the second-stage.At the same time,a code-randomized calibration algorithm is adopted to eliminate the periodic missing code phenomenon induced by the parasitic capacitance.The test results show that the DNL of the chip is-0.53 LSB⁰.78 LSB,the INL is-1.96 LSB¹.54 LSB,the ENOB is 10.21 bit,the power consumption of the entire ADC is 12 mW and the power consumption of the core module is 5 mW.4.The radiation-hardened design of Pipelined SAR ADCIn the design of the Pipelined SAR ADC chip,several radiation-hardened strategies were adopted from the aspect of layout and circuit.In terms of layout,in order to improve the ability of the ADC to resist the total ionizing dose effects,a ring-gate NMOS transistor is used and a P+guard ring is added around the NMOS transistor.In order to improve the ability of the ADC to resist single event latch-up effects,P+and N+guard rings are respectively added between the NMOS transistors and the PMOS transistors.In addition,differential charge cancellation?DCC?layout is used to mitigate the effects of single-event effects on differential analog circuits.In terms of circuit,in order to improve the ability of digital integrated circuits to resist single event transient and single event upset,dual interlocked storage cell?DICE?D flip-flops are used.The main innovations proposed in this thesis are as follows:1.A bipolar MDAC circuit with self-cancellation technique of offset voltage in residue amplifier and a weight-based digital calibration technique are proposed.The offset voltage of the comparator and the residue amplifier can cause the output voltage of the conventional unipolar MDAC to overflow.The non-linearity of the residue amplifier and the capacitor mismatch can introduce gain error.To solve these problems,a bipolar MDAC circuit with self-cancellation technique of offset voltage in residue amplifier and a weight-based digital calibration technique are proposed.Firstly,the offset voltage of±1/2 LSB of the comparator is eliminated by introducing the capacitor C_s and using the additive digital correction technique.Secondly,the offset voltage of the residue amplifier is completely eliminated by the introduction of the capacitor C_os.Finally,each carry transition point of the single-stage stage circuit is utilized to measure the actual weight of each digital code.Then the linearity of the Pipelined SAR ADC is improved.2.A V_cm-based stage circuit and its layout optimization strategy are proposed.The conventional stage circuit and the DAC capacitor mismatch can result in poor DNL and INL of the ADC.To solve this problem,a high-linearity stage circuit is proposed.Firstly,in the circuit level,A V_cm-based stage circuit is proposed.Compared with the conventional stage circuit,the DNL and INL of the V_cm-based stage circuit are reduced by about 1/2.In addition,in the layout level,a new layout of capacitor unit and a consistent routing method are proposed.A ring is created around the Metal Insulator Metal?MIM?capacitor provided by the process manufacturer.The top plate is connected by vias in the four corners.The bottom plate is connected by vias in the four sides.This routing method ensures that the ratio between each type of capacitance and the ratio between the parasitic capacitance introduced by connection is exactly the same.Then the matching degree of various capacitance of the capacitor array is improved.3.A unit bridge capacitor Pipelined SAR ADC and a code-randomized calibration algorithm are proposed.For a two-stage Pipelined SAR ADC,if the second stage uses a conventional SAR ADC,the load capacitance of the residue amplifier is exponentially related to the resolution k₂ of the second-stage SAR ADC and is 2^k2C_u.C_u is unit capacitor.Such a large load capacitance results in large power consumption of the residue amplifier.In order to solve this problem,a novel two-stage Pipelined SAR ADC is proposed in this paper.In the second stage,a unit bridge capacitor SAR ADC is used to reduce the load capacitance of the residue amplifier to 2^k2² C_u.As a result,the power consumption of the residue amplifier is reduced to the 1/2^k2 of the original power consumption.In addition,aiming at the periodic missing code phenomenon caused by the parasitic capacitance in the unit bridge capacitor SAR ADC,a code-randomized calibration algorithm is proposed.The codes of adjacent two sides of the missing codes are assigned to missing codes with the probability of 1/2,so as to compensate for the missing codes,eliminate missing code phenomenon.The research results of this thesis have important theoretical significance and engineering practical value for the development of sensor readout system and Pipelined SAR ADC chip.