CMOS RF device modeling and low-noise amplifier circuit design

The feasibility of narrowband RF circuits in advanced CMOS technologies has been studied from both device modeling and circuit design perspectives. One of the major challenges in designing CMOS RF circuits has been the lack of accurate CMOS RF transistor models. The ac models were first investigated and the discrepancies between the low-frequency mixed-mode models and the measured data were identified using a proposed set of parameters (circuit parameters). A model was proposed to improve the accuracy at RF by an additional gate resistor and a substrate network. Then the noise behavior of transistors was studied and it was found that, even at low frequencies, the conventional noise models are no longer valid for submicron CMOS devices. A noise model based on the proposed ac model was developed. Compared to the measured data, the proposed noise model shows good agreement both at low frequencies and RF.; The low-noise amplifier (LNA) was chosen as a circuit example to investigate the feasibility of CMOS RF circuit design. Different topologies were studied and it was concluded that, in narrowband RF applications, the inductively-degenerated differential common-source topology is well suited for high integration CMOS RF systems. The experimental results show CMOS technologies can be effectively used in LNA design for important applications in wireless communications, providing an accurate RF noise model is available.; The main contributions of this thesis are: (1) demonstrating the feasibility in CMOS RF circuit design. (2) proposing a way of evaluating RF device behavior by introducing circuit parameters. (3) developing a unified CMOS ac and noise model which can be used both at low-frequencies and RF. (4) investigating different circuit topologies for CMOS RF LNAs, and demonstrating a topology that is practically suitable for high integration implementations.