Research On The HPM Effects Of CMOS Inverter And GaAs HEMT Device

High power microwave(HPM) can easily couple into electronic systems through the coupling path, and further cause upset, degradation or even damage to them, posing great threat. With the development of HPM technology, the threat escalates continuously. Microelectronic device is the basic unit of electronic system, so the HPM effects on devices are fundamental to those on systems. However, the evolution trend of devices, high integration density, low power consumption, and high performance, brings the increasing HPM susceptibility of it. Hence, research on the HPM effect and mechanism on typical devices in different types of electronic systems is an essential part of HPM technology study and especially a significant task in the field of microelectronic device and circuit reliability. The conclusions in this dissertation, which may provide theoretical foundation and experimental references for the development of microelectronics and electronic information counter technology, are of great importance in practical applications.The silicon CMOS inverter and Ga As high electron mobility transistor(HEMT), respectively as the typical vulnerable device in the back door and front door path of electronic systems under the HPM action, are selected as the research objects in this dissertation. The combined method of theoretical analysis, numerical simulation and effect experiment is adopted to study the HPM effects and mechanisms. The main conclusive results are as follows:1. A simulation model of CMOS inverter based on 0.5 μm technology is established by Sentaurus-TCAD, and meanwhile the equivalent signal of HPM is constructed. The HPM induced malfunction effect and power supply current characteristic are acquired by simulation. The transient response and interior physical quantity distribution are studied. The results indicate that the upset effect is due to that the HPM triggers latch-up in inverter and hence a large current path with low impedance from the power trail to ground occurs. Analysis of the thermal effect demonstrates the hot spot within the device will transfer from one location to another over time under the HPM action. The HPM induced direct damage effect on CMOS inverter is studied and the damage threshold changing law and the corresponding empirical formula are acquired.2. Based on the simulation model of CMOS inverter, temperature dependence on HPM upset effect is studied. The study result indicates that CMOS inverter operating at higher ambient temperature is more susceptible to HPM, which is verified by the experimental data and meanwhile expands the application temperature range. The analysis suggests that the increased susceptibility at higher ambient temperature is attributed to an increase in substrate resistance. The HPM induced latch-up delay time characteristic is acquired by simulation. The influence of temperature distribution is analyzed and the result reveals that the delay time characteristic is closely related to the thermal boundary condition. Specifically, the average temperature continuously rising leads to an increase in impedance in the large current path, and thence the latch-up becomes difficult to maintain. This conclusion provides a microscopic interpretation of the latch-up delay time characteristic reported by literature.3. From the analysis of the HPM upset effect mechanism, the analytical models of the HPM upset threshold regarding HPM pulse-width effect and frequency influence are derived and verified by the simulated results and experimental data. The research suggests that the HPM caused excess carriers injection dominates the current amplification process of the parasitic transistor, which is vital to the upset effect. The HPM upset pulse-width effect can be interpreted by the excess carriers accumulation in the base of the parasitic transistor. And the influence of HPM frequency on upset effect is owing to the fact that the AC field within the CMOS inverter varies too rapidly for the carriers to follow at high frequency, which affects the total injected charge and excess carriers distribution. The influence of device layout parameter LB on upset effect is explored using the analytical model. It is found that CMOS inverter with minor LB is more susceptible to HPM, which is verified by simulated results.4. The simulation model of Ga As p HEMT with double δ-doping structure is constructed, and the model parameters are corrected. The DC characteristics curves are obtained by simulation. The HPM induced damage and degradation in HEMT and the mechanisms are studied in detail. The study results indicate that the mechanism of HPM damage to Ga As HEMT is that emerging current path and strong electric field beneath the gate metal near the source contact cause the temperature continuously rising so that the burnout of HEMT happens. The HPM pulse-width effect of Ga As HEMT and the empirical formula of the effect are acquired by simulation and data processing. Analysis suggests that the HPM\could lead to the gate metal diffusion and hence the Schottky junction may be physically degraded. Simulated results reveal that the HPM induced structure degradation will result in drain saturation current decreasing, transfer characteristic curve positively drifting, cut-off voltage increasing, peak transconductance increasing, and small-signal gain being obviously degraded.5. A series of HPM injection experiments are carried out on the dual-stage Ga As HEMT cascaded low noise amplifiers(LNAs). Experimental results indicate that LNA will be degraded in small-signal gain or even severely damaged by HPM, and the degradation and damage are demonstrated to be unrecoverable and permanent. The noise figure(NF) of LNA is also found to be sensitive to the HPM injection power, while the output power and real-time gain are not sensitive to that at all. The degradation and damage threshold of LNA are acquired from experimental results. The damage threshold changing law agrees well with the empirical formula obtained by simulation. Besides, the HPM degradation of LNA also behaves as pulse-width effect. Specifically, the degradation threshold increases with the pulse-width decreasing, and nonetheless LNA will be directly damaged instead of firstly degraded if the HPM duration is short enough. Failure analysis demonstrates the HPM induced failure of LNA is due to the failure of first stage HEMT. The chip surface morphology features obtained by metallographic microscope and scanning electron microscope(SEM) reveal that thermal breakdown spot appears near the gate metallization close to the source contact of the first stage HEMT, in accordance with simulated results and the mechanism analysis of HPM damage. The SEM feature of the first stage HEMT of degraded LNA shows that unusual pits exist underneath the gate metallization, providing physical evidence for the mechanism analysis of HPM degradation.