Research And Design Of A Silicon Cmos Low Noise Amplifier

Wireless communications technology through the development of a short span of several decades has been throughout all aspect of human society, and its broad application. With the rapid development of science technology and the further rhythm of life, it becomes more rougher on wireless communication technology, radio-frequency(RF)and communication integrated circuit. All countries of the world increase the research in wireless communications technology.RF receiver circuit of wireless communication technology is the most important part in the entire system. As the first stage of the RF transceiver, LNA is a one of key component, its noise, gain and linearity performance will take a significant impact to the whole system, directly. On how to meet the requirements to design low-noise amplifier has a practical significance.At past most low-noise amplifier using GaAs process, but because of GaAs technology and not compatible with Silicon-CMOS technology, the miniaturization and integrated of circuit can't be realized. The problem with the rapid development of CMOS process can be improved, the use of CMOS technology allows the realization of RF front-end and digital back-end circuit of the monolithic integration can be achieved. With the rapid development of wireless communications, the tendency of RF circuit is: small size, low power, low cost, high performance and high integration. Continuous improvement of the CMOS technology can be very good to meet such developments. At present, CMOS low noise amplifier technology has become a focus on analog circuits.This thesis firstly describes the electrical characteristics of CMOS devices. And then make a introduction in detail for the key performance parameters of noise and linearity of the Low-noise amplifier. Based on the analysis of MOSFET two-port noise network, several common low-noise amplifier topology be illustrated. Make a detailed analysis of the most popular topology structure of LNA which is the source inductor degeneration, and introduced a mid inductor to the classic cascode topology to improve the linearity and voltage gain. Using power constrained noise optimization technology, will enable LNA obtain the optimal noise characteristics under specific power consumption.At the end,this thesis gives an example of a LNA that based on Shanghai huahong-NEC's 0.35μm CMOS process, which is a full monolithic integrated LNA with 3.3V supply voltage is presented, and work frequency is 2GHz. Optimize the circuit structure and the parameter of components by analyzing the simulation results of the LNA. Finally the LNA power gain is 13dB and noise figure is 1.9dB, this result shows the designed LNA have a good performance, complying with the design request.