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Physical modeling and analysis of deep-submicron silicon-on-insulator CMOS devices and circuits

Posted on:2000-06-23Degree:Ph.DType:Dissertation
University:University of FloridaCandidate:Workman, Glenn Orrick, IVFull Text:PDF
GTID:1468390014462489Subject:Engineering
Abstract/Summary:
This dissertation focuses on the modeling of scaled silicon-on-insulator (SOI) complementary metal-oxide-semiconductor (CMOS) field-effect transistors (FETs). Refinements and additions to the University of Florida SOI fully depleted (FD) and partially depleted (or non-fully depleted, NFD) SOI MOSFET models are developed and applied to gain insight into the behavior of SOI MOSFETs in integrated circuits.;Refined parasitic junction current and charge models result in more accurate simulation of body effects, and models for reverse short-channel and narrow-width effects result in broader applicability over the wide device-geometry range typical of contemporary CMOS technologies. A physical model for temperature dependence is implemented and exercised to gain insight into the temperature sensitivity of body effects. The importance of physical modeling to properly account for self-heating in model parameter calibration is illustrated. A study of the body-tied-to-gate NFD device shows performance advantages in some low-voltage applications, but also identifies non-ideal behavior associated with the body resistance, which must be considered in circuit design.;A physics-based model for noise behavior is implemented and shown to accurately portray a unique Lorentzian-shaped excess noise component exhibited by SOI MOSFETs. Insight on the origin of this excess noise leads to the novel concept of creating an FD device from a nearly-FD technology which is free of all floating-body effects over a wide bias range. A model is presented that accounts for the effects of non-local carrier heating on the thermal channel noise. The presence of hot carriers is shown to impact the noise performance of a low-voltage SOI low-noise amplifier (LNA) operating at 13GHz. An n-lump non-quasi-static model is utilized to study the applicability of the quasi-static channel thermal noise model at high frequencies. It is shown that although the noise model does not accurately portray the channel-induced gate noise at any frequency, this noise component is inconsequential in circuits (e.g., the LNA) operating well below the device cutoff frequency.
Keywords/Search Tags:Model, CMOS, SOI, Noise, Device, Physical
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