Analyse et conception des circuits de synthese numerique d'horloges (French and English text)

This thesis explores efficient methods to synchronize two clocks having different frequencies that are linked by arbitrary rational divide ratios. The synchronization methods described in this thesis are based on the generation of a clock having the desired frequency, by using another clock as a reference frequency. The divide ratio between the reference frequency and the desired frequency is given by an arbitrary rational number.; Previous studies have shown that phase accumulators can be used to generate clocks that have a frequency controlled digitally, with a high precision. Our goal is to implement clock synthesis circuits that can produce frequencies up to 500MHz, with a jitter smaller than 400ps. Those performances are required by digital television standards.; We propose a jitter model for direct digital synthesis circuits (DDS). This model describes the value of the output jitter of a DDS circuit depending on the design parameters. It can be used to make optimal design decisions. We then propose a correction method for the error produced by the phase accumulators used to synchronize clocks having frequencies related by arbitrary divide ratios. The jitter model and the correction method have been verified by implementing a DDS circuit using 0.35 microns CMOS technology.; Finally, we propose a direct digital period synthesis (DDPS) circuit that can surpass the standard DDS circuits, in terms of output frequency and low jitter. This circuit has been realized in 0.25 micron CMOS technology. It has produced experimental results superior to known DDS solutions. This kind of circuit is ideal for synchronization and clock synthesis problems; its applications include digital television, cellular phone systems, radar systems, fast processors and all other applications that require a high output frequency and a low jitter.