Analysis And Compensation Of Effect Caused By Non-Ideal Sampling Clock Characteristics In Broadband OFDM Trial System

With fierce competition among various communication standards and spectrum shortness, software programming realization based on uniform hardware platform in SDR (Software Defined Radio) have drawn more and more attention. One foundation of SDR is high-speed signal sampling in analog front end. Also the demand of broadband high-speed transmission makes OFDM a core technology for new generation digital mobile communication systems. High quality of sampling clock required by high-speed signal sampling and sensitivity towards frequency deviation of OFDM technology make the research of sampling clock in the broadband OFDM trial system particularly necessary.The sampling clock characteristics and its specific effects to the broadband OFDM trial system are studied in this thesis. Firstly the research foundation, such as OFDM technology and A/D conversion principles, are introduced. Then the effects of the sampling clock features on the trial system hardware structure and the algorithm structure are studied respectively. The main contents of this thesis are as follows:According to the effect of the sampling clock’s jitter on trial system’s hardware performance, the relationship between the output signal’s signal-to-noise ratio (SNR) of A/D converter and the sampling clock jitter is mainly studied in the thesis. After the introduction of the clock reference indicators, detailed analyses of the trial system clock input and clock processing circuit, as well as the test results of the clock performance in the trial system are provided. Then this thesis theoretically analyzes the effect of sampling clock jitter on ADC output signal-to-noise ratio. Combined with ADC chips used in the trial system, the attenuation caused by clock jitter in ideal state is analysed. Finally it gives the test condition and method of ADC performance testing, tests the ADC performance and gives the overall analysis results.As for the effect of the sampling clock’s non-ideal characteristics on systematic algorithm performance, the thesis mainly studies the effect of sampling clock frequency deviation on OFDM technology. First it analyzes the phase rotation and inter-carrier interference of the OFDM sub-carriers caused by the clock frequency deviation, and carries on a deviation test for the trial system which verifies the conclusions of theoretical derivation. Then two common clock synchronization and deviation compensation method are analyzed. Finally, the thesis gives the schemes of sampling frequency deviation synchronization for fixed clock and variable clock respectively, which is implemented on FPGA in the trial system.