The Design And Realization Of A Low Jitter 1-to-32 Multiplier Pll

With the development of System-on-Chip (SOC), phase-locked loops are widely used to generate on-chip clocks in high-performance digital systems. The diversity of applications has also led to require diversity in operating frequencies of PLL. As the increasing of system frequency, the system performance is much more sensitive to the jitter of the clock. It is defined as the deviation over time in the output clock edge time locations from those of an ideal clock output that is perfectly periodic. The output clock should track the input clock as close as possible to minimize long-term jitter.In this paper, a low jitter 1-to-32 multiplier PLL with frequence from 120MHz to 1200MHz is designed in 0.13μm CMOS logic technology with 1.2V power supply.The dissertation first describes the principle of Charge Pump PLL and analyzes the definition of jitter from the view of an engineer. Then a new architecture for self-biased PLL is achieved. The most important factors attached to output jitter are investigated.In the circuit design of PLL, paper made full use of the method based on circuit structure optimization to reduce the jitter of the PLL with the analysis of the adaptive bandwidth. Furthermore, a new charge pump circuit is designed in this paper to achieve the changing divider PLL.In the layout placement, paper layouts every modules in reason to reduce the area as well as reducing the jitter of the PLL with the high-speed layout design of mixed technology.Layout post simulation has shown that PLL output clock has very good jitter performance; the peak-to-peak value of long-term jitter is 56.447ps under the typical frequency 300MHz, which satisfies the expected design requirement.