Fault diagnosis in scan-BIST with system-on-chip applications

The goal of fault diagnosis in integrated circuits (ICs) is to identify the physical location of a defect, commonly referred to as a fault. The cost of diagnosis is measured by the time and hardware resources required for fault location, and the quality of diagnosis is characterized by diagnostic resolution, which is intuitively defined as the ability to determine a small set of candidate faults. However, the diagnosis of complex ICs with a scan-based built-in-self-test (BIST) architecture is challenging because of the large number of test patterns and circuit components. High resolution requires excessive diagnosis cost, and traditional diagnostic methods fail to provide fine-grained diagnostic resolution and reduced time-to-market for today's complex ICs.; This thesis presents a set of new techniques for fault diagnosis, especially in a scan-BIST environment. These techniques include new interval-based approaches for the identification of failing test patterns and error-capturing flip-flops, and new methods for creating highly-compacted fault dictionaries without losing diagnostic resolution.; A new scan-BIST approach for determining failing vectors for fault diagnosis is first described. This approach is based on the application of overlapping intervals of test vectors to the circuit under test. A signature analysis method for overlapping sections to effectively prune the candidate set is also introduced.; Next, a new technique for generating compact dictionaries for cause-effect diagnosis in scan-BIST is presented. This approach relies on the use of LFSR-based and interval-based compact dictionaries. A combination of three compact dictionaries can be used to obtain two to three orders of magnitude reduction in memory requirements without compromising diagnostic resolution. Next, dictionary compaction techniques are presented to facilitate the use of scoring algorithms for the diagnosis of unmodeled faults. It is shown that these compact dictionaries can be used to efficiently locate unmodeled faults using scoring algorithms.; Diagnosis issues for system-on-a-chip (SOC) integrated circuits are also addressed in this thesis. Fault diagnosis in SOCs from a system perspective is challenging and not well-understood. A new partitioning scheme for the identification of failing (error-capturing) flip-flops in scan-BIST is presented. This approach relies on a two-step scan chain partitioning scheme and it is especially suitable for an SOC composed of multiple embedded cores.; Finally, a new approach is presented for identifying faulty embedded cores in SOCs. The proposed technique is based on the use of multiple test sessions and a careful assignment of cores to test sessions. The problem of identifying a failing core with minimum test application time is formulated as an optimization problem and both exact method and fast heuristic methods are described to solve this problem.; In summary, this thesis presents several solutions to fault diagnosis using scan-BIST architectures. These techniques are expected to reduce diagnosis cost and enhance yield learning by providing higher resolution with less test application time and memory requirements.