A method of constructive test point insertion for scan-based built-in self-test

A new testing paradigm called Built-In Self-Test (BIST) has been gaining increasing acceptance over the traditional automatic test pattern generation for testing the current complex integrated circuits. The basic idea in BIST is to integrate the design with test functionalities like pattern generation, response analysis, and test control. Of the various schemes, pseudo-random pattern testing is an attractive technique for BIST because of the simple hardware required for on-chip test pattern generation. Besides, structures for pseudo-random pattern generation like linear feedback shift register (LFSR) or cellular automata (CA) can also be utilized for on-chip response analysis.; In general, pseudo-random BIST is effective only for combinational circuits. This is due to the difficulty associated in obtaining a specific sequence of vectors, through a pseudo-random source, that may be necessary for detecting a fault in a sequential circuit. Thus during test mode, the circuit-under-test (CUT) is transformed to a combinational circuit by configuring memory elements into scan chain(s). However, this may not suffice for circuits that contain random pattern resistant faults or faults not easily detected by random patterns.; Two distinct classes of solutions have been proposed to address the random pattern resistance problem--those that modify input patterns and those that modify the CUT. This thesis presents a new, effective circuit modification method for scan-based BIST of integrated circuits. The proposed circuit modification technique utilizes control and observation points to improve the fault coverage, much like the previous techniques. However, unlike the previous methods, the proposed technique is based on a constructive methodology. A divide and conquer approach is used to partition the entire test into multiple phases. In each phase control/observation points targeting a specific set of undetected faults are identified utilizing a new technique called probabilistic fault simulation. This technique blends fault-free simulation and analytical forward fault propagation to accurately compute the information necessary for the identification of control/observation points.; Observation points in the proposed scheme are kept enabled for the entire test. However, control points are enabled during specific test phases by fixed values. The usage of fixed values leads to a simple and inherent sharing of the logic driving them. This sharing, as well as the reduction of number of control points result in significant reduction in area overhead. Furthermore, fixed values reduce power dissipation during test mode, since control points instead of toggling are set to a constant value during the entire phase.; Experimental results indicate that complete or near-complete stuck-at fault coverage can be achieved by the proposed technique with the insertion of few test points and phases. Results show that modification of less than 1% of circuit nodes is sufficient to achieve complete coverage or greater than 99% coverage. In addition, the proposed techniques are fast and hence are applicable to large circuits.