Research Of Testing Algorithm And BIST Based On Boundary Scan Technology

With the development of intergrated circuit, it is difficult to test the complicated circuit quickly and efficaciously based on traditional testing method. As a standard technique of Design-For-Test for the circuit boards, Boundary-Scan technique can improve the testability and controllability of complex digital circuits effectively by embedding special boundary scan cells inside the circuits. As widely application of boundary scan chips, it is very important to research the theory of Boundary-Scan Tesing and develop a testing system based on the technology in order to enhance the testability and reduce the cost of the electronic equipment maintenance.The major tasks of the thesis are research the algorithm of interconnect tesing, the theory of BIST based on boundary scan and developing the boundary scan tesing system. Through research the existing interconnect testing algorithms, we develop a optimizing algorithm, making the generated set of test vectors has a good balance between testing time and fault diagnostic capabilities. Interconnect tesing can't diagnose the malfunction of logic function, so we design the scheme of BIST based on boundary scan, focusing on the pseudorandom testing design to achieve logic function testing. In order to verify the testing theory, we develop the boundary scan tesing system. The system consists of a boundary scan testing card and testing software. The tesing software can automaticly complete the tasks of vector-generate, vector-download, response-analyse and so on. The testing vectors by testing algorithm, Net-File and BSDL. The boundary scan testing card translates the tesing command sand vectors to control signals according to the IEEE 1149.1 Std.Finally, we use the testing system to complete the experiments of interconnect testing and BIST based on boundary scan. The tesing system can effectively detect and diagnose the malfunction of circuits according to the experiment results. The results also prove the Interconnect testing algorithm and the scheme of BIST mentioned in this thesis.