The Design For Test And Implementation Of Microprocessor

JX5 is a complex microprocessor, which contains cache , microcode ROM , instruction prefetch unit,instruction decode unit,integer unit,MMX unit,floating point unit, page unit,bus unit,DP logic, APIC and so on.It is very difficulty to test a such complicated microprocessor and receive anticipative fault coverage ratio.So,we must add DFT in CPU'design.In this paper, based on the study of all kinds of technologies and ways of design for testability prevailing currently in the world, a scheme of design for testability is proposed aimed at JX5 microprocessor's features and specified test requirements. This scheme fully considers the internal structure of JX5 microprocessor, at the same time, the processor's processing ability, address and data bus architecture is efficiently utilized. So with the minimal testing cost, a strong fault testing and trace debugging ability is provided to meet the JX5 processor's testing demand. Finally the author constructs the full testing structure of JX5 microprocessor and implements it independently.JX5 microprocessor's testing structure comprises built-in self-test(BIST), boundary scan and internal scan. BIST tests processor's microcode ROM, and other RAMs are tested through the execution of the program in the microcode ROM. And more than 70% hardware are tested during microcode self-test since the execution of micro program can cover other data paths. Boundary scan is designed according to IEEE1149.1, and some other instructions such as DEGUG, RUNBIST are provided to support internal fault testing, online debugging and built-in self-test besides the several necessary insructions. Internal scan is implemented by partial scan, through this the boundary of logic component and user-cared system registers can be selected to be scanned. This structure not only achieves the purpose of hardware logic partition but also makes it convenient for the generation of test stimulus, fault simulation, and online debugging. Furthermore,we make internal scan share the test access port, so the pin's cost which brings for test is reduced.