Research Of Test Generation Platform For Digital Circuits And Application Of DFT

With the continuing development of integrated circuits, researches of Design for Test and Automatic Test Pattern Generation become more and more important.This thesis firstly studies fundamentals of digital circuits tests, methods of DFT and various algorithms of ATPG, especially the PODEM algorithm that is one of deterministic test generation algorithms. Based on the solid understanding of PODEM algorithm, this thesis develops a digital circuits test generation platform, which can be used for researching of test vectors, and it runs under Windows OS. The platform reads in net list files of circuits and analyzes the structures of them, computes the controlability and observability for all the nodes in them, and at last generates the deterministic test patterns as well as the fault coverage report for the circuits.The thesis also studies the pseudo-random pattern generation (PRPG) technology which has been widespread used currently, introduces the LFSR method for PRPG, and based on this platform, analyzes and compares the test efficiency of pseudo random test patterns and deterministic test patterns.In addition, the thesis makes a further step to summarize the scan design, build-in-self-test, boundary scan and testable design technologies for digital IP cores. What's more, it applies the boundary scan technology to an embedded MCU core, adding an IEEE 1149.1 standard compatible test port, a TAP controller and a boundary scan chain to it. These components have improved the testability of the MCU. In the mean time, the thesis introduces an error checking and correction module to general BIST technology for memory, and the simulation results indicate that as well as the self test ability of memory devices in systems, this design can also verify data storages in normal working status, improving the stability of storage systems.