A Low Power CMOS Design of An All Digital Phase Locked Loop

This dissertation presents a proposed all digital phase locked loop and a digitally controlled oscillator with low power consumption for fractional-N frequency synthesis applications. The basic operation of the conventional PLL-based frequency synthesizers is first briefly reviewed, followed by the literature review of some reported digital PLL based frequency synthesizer. An all digital PLL is thus proposed, including the system architecture and implementations of its sub-blocks. In the proposed all digital PLL, the PFD-TDC pair used in many reported digital PLLs is replaced by a customized time-to-digital converter. A novel Schmitt trigger based digital controlled oscillator is proposed to achieve a wide linear tuning range with low power consumption.;The novel locking process of the proposed ADPLL is separated into frequency and phase acquisition. Instead of "ahead" or "behind" comparison, the time-to-digital converter is used to measure the frequency difference accurately, which greatly reduces the lock-in time. The phase acquisition only takes two reference clocks. One cycle for resetting the DCO and the other cycle for updating the control considering the path delay.;To further prove the feasibility of the novel ADPLL, a fractional-N frequency synthesizer is implemented based on the proposed ADPLL. An extra TDC is applied to obtain the fractional value avoiding the use of fractional divider, which is the main source of fractional spur in a fractional-N frequency synthesizer. The proposed Fractional-N frequency synthesizer is implemented using a 0.9V 32nm Practical Transistor Model. The phase noise performance, the frequency locking speed as well as the tuning range of the digitally controlled oscillator was measured and well agrees with the theoretical analysis.