| Frequency synthesizer is a critical module in the radio frequency system. Nowadays All Digital Phase Locked Loop (ADPLL) is gradually becoming the new preferable choice for circuits design and drawing more and more attention from researchers. Compared to the traditional analog frequency synthesizer, ADPLL provide a better solution to such problems as low voltage and device mismatch with a smaller chip area. And what’s more important, ADPLL is more adapt to the advanced CMOS technology. As a critical apart of the ADPLL system, digital controlled LC oscillator is also attracting more and more attention.A digital controlled LC oscillator used in all digital phase locked loop is introduced in this article. After frequency dividing, the output frequency channel of the oscillator can be used in the high speed wireless bcal area network of IEEE802.11a. According to the system design request, phase noise and frequency resolution of the oscillator are the most important specifications. In order to reduce the output phase noise of the oscillator, a complementary structure instead of all-NMOS one is used, as well as the second harmonic filtering technology. What’s more, the PMOS-NMOS varactor is used in order to achieve the frequency resolution of40KHz of the oscillator to effectively reduce the high frequency noise of the synthesizer.A digital-controlled LC oscillator is implemented in TSMC65nm CMOS process, which is used in all digital frequency synthesizer with an output frequency ranging from8.95GHz to11.02GHz. In order to reduce the phase noise, the complementary structure with tail inductors is used. The capacitor banks are divided into three parts in order to coordinate with the three steps of frequency locking process of the synthesizer. Under a supply of IV the power consumption is3.53mW. According to the measurement result, a frequency resolution of40KHz is realized and the phase noise at9.38GHz is-111.02dBc/Hzat1MHzoffeet... |
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