Effects of non-uniform substrate temperature in high-performance integrated circuits: Modeling, analysis, and implications for signal integrity and interconnect performance optimization

The ever-increasing demand for complex ULSI (Ultra Large Scale Integration) circuits with higher performance is leading to higher clock frequencies and device packing density, which results in large on-chip power dissipation. The large power consumption results in dramatic increase in device junction temperature. Furthermore, different switching activities and/or sleep modes of various functional blocks and dynamic power management policies can be major sources of thermal non-uniformities over the Silicon substrate. Without adequate thermal engineering, significant non-uniform temperature distributions can lead to considerable interconnect thermal gradients and substrate hot-spots. Hence, thermal management is essential to the development of future generations of microprocessors, integrated network processors, and systems-on-a-chip (SOC). At the circuit level, temperature variations in the substrate and interconnect lines have important implications for circuit performance and reliability.; The research presented in this thesis focuses on analysis and modeling of non-uniform chip temperature profile and the study of its effects on different aspects of signal integrity and performance in very high-performance ULSI designs. This dissertation makes contributions in four distinct, yet related, areas. First, a detailed analysis of the interconnect temperature distributions in the presence of non-uniform substrate thermal profiles is presented. To study the effect of non-uniform substrate temperature on the signal performance in interconnects, a non-uniform temperature-dependent distributed RC interconnect delay model is proposed. Second, by using the proposed temperature-dependent RC delay model, it is shown that clock distribution networks are one of the most vulnerable signal nets to the substrate thermal non-uniformities. Subsequently, a thermally driven near-zero-skew clock routing methodology is proposed. Third, it is shown that the non-uniform substrate temperatures can affect the optimal buffer insertion techniques. Consequently, a new design methodology is provided to reduce the impact of these effects on the optimality of the buffer insertion. Finally, the effects of substrate hot-spots and technology scaling on the worst-case power distribution network voltage (IR) drop are examined. By introducing these studies and methodologies for the first time, it is shown how the presence of substrate non-uniform temperatures can severely degrade the performance of the circuits resulting from conventional design flows.