Optimal signal, power, clock and thermal interconnect networks for high-performance two-dimensional and three-dimensional integrated circuits

A high-performance 2D or 3D integrated circuit typically has (i) ratio of delay of a 1mm wire to delay of a nMOS transistor >500, (ii) target impedance of power delivery network <1mO, (iii) clock frequency >2GHz, and (iv) thermal resistance requirement of heat removal path < 0.6°C/W. This data illustrates the difficulty of obtaining high-quality signal, power, clock and thermal interconnect networks for gigascale 2D and 3D integrated circuits. Specific material, process, circuit, packaging, and architecture solutions to enhance these four types of interconnect networks are proposed and quantitatively evaluated. A microchannel-cooled 3D integrated circuit technology is developed to deal with thermal interconnect problems inherent to stacked dice. The benefits of carbon nanotube technology, improved repeater insertion techniques and parallel processing architectures for signal interconnect networks are evaluated. A circuit technique to periodically reverse current direction in power interconnect networks is proposed. It provides several orders of magnitude improvement in electromigration lifetimes. Methods to control power supply noise and reduce its impact on clock interconnect networks are investigated. Finally, a CAD tool to co-design signal, power, clock and thermal interconnect networks in high-performance 2D and 3D integrated circuits is developed.