Analysis Of Interconnect Performance Considering Non-Uniform Temperature Effects

With the development of the VLSI technology, Interconnect system has become the decision factor of system performance and power consumption, and the interconnect thermal issue has an significant influence on chip design and reliability. This paper focuses on non-uniform substrate temperature effects in the interconnect. First, several different substrate temperature distribution models and its interconnect RC delay model are being analyzed. Then, On the basis of introducing the thermal non-uniformities and using the temperature-dependent RC delay model, the temperature-dependent RC interconnect delay model which guarantees a near zero skew clock is successfully proposed and built. Finally, in the temperature-dependent RC interconnect delay model, the effects of temperature on the interconnect line and the inserted buffer dramatically changes the optimality of the conventional buffer insertion techniques. These non-uniform thermal effects become more and more serious and must be taken into account in the design methodology to ensure near optimality of the performance.