Performance Optimization Of Interconnect Considering Self-heating Effect And Thermal Transfer Analysis For TSV

As the feature sizes of integrate circuits decrease to nanometer，the chip featuresize continues to decrease while integration level is improved continuously. Theincrease of the number of transistors enhances the complexity of chip. Theinterconnection, which connects function modules on chip, is becoming more complexas well. The centre of the design integrated circuit (IC) has shifted from electronicdevice to the interconnection. Variation of interconnect wire resistance, which resultsfrom the influence of temperature, and the adopting of new materials with low thermalconductivity lead to the deterioration of performance and reliability of the circuit. Thethermal problems of chip always restrict the development of IC. Consequently, theresearch of interconnection performance with consideration of the self-heating effect ofinterconnect is necessary.At present the number of metal layer has reached13in nanometer integratedcircuit, which result in a longer path between the interconnect wire and the substrateattached to heat sink for the heat dissipation of interconnection. In addition, adoption oflow dielectric constant materials in IC manufacture makes the interconnection heatmore difficult to dissipate. Interconnection Joule’s heat increases the interconnectiontemperature while seriously affects the accuracy of interconnection performanceestimation. The research centered on the effect of self-heating, interconnectionperformance optimization and thermal management of3D ICs. The main studies andconclusive results are as follows:(1) For single interconnect wire, a non-uniform interconnection structure whichcan low the interconnection delay effectively is introduced. Then the non-uniforminterconnection contribution on power reduction is proved. Based on the two-portnetwork current and voltage theory, the input and output current and voltage are derived.Last the energy consumptions distribution model of the interconnect circuit whichincludes front-end driver and back-end load. The proposed model is simulated at65nmCMOS technology. The concluded output voltage accords well with the simulationresult of HSPICE. Simulation results of the energy consumption are analyzed withdifferent interconnect wire length and different load capacitor. The energy consumptionsdistribution model is more applicable to long wire and large load capacitor forinterconnection. Compared with uniform interconnection, the adoption of non-uniforminterconnection structure works well on power optimization.(2) Based on the distributed interconnect power model, a novel dynamic power model is presented in this paper, which adopts a non-uniform interconnection structure.This model takes into account the self-heating effect and is constrained by delay,bandwidth, area, minimum interconnect width and minimum interconnect space. Thevalidity of the proposed model is verified at90nm and65nm CMOS technology. Theresults indicated that the proposed model can generate a power consumption reductionas high as35%, and yet the delay, area, bandwidth are not deteriorated, compared withthe conventional power model. The simulation results indicates that the proposed modelis more applicable to the interconnect circuit which has low load capacitance and largedriver resistance. The proposed optimal model can be used for design of large scaleinterconnect router and clock network in network-on-chip structure.(3) The interconnection which needed buffer insertion is a long global line. As it islocated far away from heat sink, the global interconnect has poor heat dissipationcapacity. Therefore, the self-heating effect greatly affects interconnect performance andelectromigration reliability. For traditional optimal buffer insertion, the model is basedon a constant temperature assumption. In order to resolve the shortage, the interconnectresistance per unit length is modification with the consideration of the sealf-heatingeffect since the interconnect resistance has a linear dependence on the temperature. Byusing the graphical mythologies, the relationships between sealf-heating effect and delay,bandwidth, power and area are analyzed. For the purpose of having a small delay, powerdissipation and area while having a large bandwidth, a general metric for the tradeoff onall of above performance is developed. The proposed optimal model is verified andcompared based on90nm,65nm and40nm CMOS technologies. It is found that thevalues of wopt, sopt, koptand hoptare larger than that of no considering the self-heatingeffect. More optimum results can be easily obtained by the proposed model. Thisoptimization model is more accurate and realistic than the conventional optimizationmodels, and can be integrated into the global interconnection design of nano-scaleintegrated circuits.(4) One of the most important benefits of three-dimensional (3D) architecture overa traditional two-dimensional (2-D) design is the reduction in global interconnects andtotal wire-length, thereby providing higher timing performance and lower powerconsumption. Further, a3-D integrated system can include multiple design disciplines(Digital, analog, RF) and disparate process technologies (SOI, SiGe, GaAs, etc.), thatextend the capabilities of the3D system, expanding the boundaries of the IC designspace. Of all the development-hampering factors for3D ICs, thermal management is undoubtedly the most important factors. Based on the one-dimensional heat transfermodel proposed by Ankur Jain, a3D analytical heat transfer model for3D ICs withthrough silicon via (TSV) is developed in this paper. The simulation results areconsistent with the result based on ANSYS. The results of analysis indicate thatincreasing insertion density of TSV, and radius of TSV, decreasing the thickness of backend of line and adopting TSV insertion of higher thermal conductivity can effectivelyimprove the heat dissipation of3D ICs circuits. It is proved that the importance of TSVin thermal diffusion for3D ICs. Meanwhile, The effects of the horizontal heat transferon the thermal management of3D ICs is analyzed when the number of strata, the TSVdensity, the TSV diameter and the thickness of the BEOL layer vary under the specificprocess and thermal parameters. The results indicated that the temperature rise,simulated by the model presented in this paper, is lower compared with the conditionwithout considering the horizontal heat transfer effect. The difference of the temperaturecan be above10%. And the effect of the horizontal heat transfer on the thermalmanagement of3D ICs is more obvious with the increase of integrated level. Since themodel presented in this paper conforms to the actual situation, it can be more accurate inanalyzing the temperatures of stacked chips in3D ICs.