Temperature Effect And Performance Optimization Of Nanoscale Interconnect

As the integrated circuit technology scales into nanometer regime, the increasingly significant interconnect temperature effect is becoming one of the most challenging problems in IC design. In this paper, the analysis and optimization of the nanoscale temperature effect is mainly studied.On the basis of interconnect resistance, capacitance and inductance parasitic parameters, the proper heat transfer model for IC interconnect structure is established. According to top-level interconnect and other interconnect layers, their temperature distribution expressions and interconnect reliability are analyzed. Considering that the interconnect reliability is decreased with the large power consumption and high interconnect temperature. A figure of merit (FOM) is defined with the interconnect delay, interconnect power consumption and bandwidth factors into consideration. By maximizing FOM, a lower repeater supply voltage and a higher threshold voltage can be obtained to optimize the global interconnect performance.The results show that, compared with traditional single supply voltage and single threshold voltage method, interconnect power and interconnect temperature can be reduced by the dual-voltage interconnect method, and the circuit reliability can be improved.