Design of advanced I/O interconnect circuits and systems in CMOS

As the need for higher communicational performance grows in modern digital systems, the major challenge of inter-chip communications is to design interconnect architectures and signaling technologies that can support high throughput, high concurrency, as well as low latency. Excessive I/O signaling power dissipation is also becoming a critical factor in low-power digital system design.; This dissertation presents design techniques for advanced interconnect circuits and systems to exploit parallelism in inter-chip communications. To improve the system performance without increasing communication resources, a new latency-aware PO interface technology named source synchronous CDMA interconnect (SSCDMA-I), which focuses on latency rather than bandwidth, is proposed. By utilizing 2-bit orthogonal CDMA coding and source synchronous clocking, a single 3-level SSCDMA-I channel operates as if it consists of dual virtual time-multiplexed channels. Therefore, a single SSCDMA-I enables dual concurrent transactions on a shared bus or link, which results in reduced request latency and increased concurrency without increasing the number of pins and wires. The chips fabricated in a 0.18-mum CMOS technology and the test board demonstrated a data rate of 2.5 Gbps/pin between four off-chip I/Os. To evaluate the system-level performance, a SSCDMA-I bus-based multi-core system was modeled and simulated with a cycle-accurate GEZEL co-simulation kernel. Compared to a conventional bus-based SMP system, SSCDMA-I improves the system performance up to 23.1% by reducing the bus contention interferences from simultaneous traffic loads.; This dissertation also presents a low-power interconnect technology: capacitive coupled pulsed signaling bus interface (CCBI) on a fully AC coupled multi-point bus. CCBI has no DC power component unlike conventional square wave signaling. The CCBI transceiver, fabricated in 0.10-mum CMOS with a WBGA package, achieves 1 Gbps over a 10-cm FR4 PCB and dissipates 2.9 mW (2.9 pJ/bit) for the driver and channel termination. By using on-chip capacitive coupling, the fully AC coupled bus topology reduces the impedance discontinuity and ISI and therefore increases the available channel bandwidth. This technique consumes 7.5 times less energy/bit than current state-of-the-art memory bus interfaces, demonstrating a method of improving signal integrity with less signaling power.