Interconnect modeling, signal integrity and reliability analysis for deep sub-micron integrated circuits

Interconnect parasitics contribute to more than 50 percent of circuit delay in Deep Sub-Micron (DSM) technologies. Signal integrity and reliability issues contribute to more than 25 percent of circuit failures in DSM designs. This research covers a detailed study in accurate modeling of interconnect parasitics, and of their effects on signal integrity and reliability of the System-On-Chip (SOC) class of DSM designs. Anomalies in interconnect capacitance in copper and low-k technologies and techniques to address these are presented. A new paradigm of timing-driven parasitic extraction is introduced to address accuracy issues in interconnect modeling. Novel techniques for silicon validation of parasitic capacitance and inductance are presented. New interconnect benchmarks are proposed to enable development and comparison of interconnect modeling techniques. A practical method to model process variations and analyze their impact on signal integrity is discussed. A detailed study of inductance modeling and its impact on signal integrity is presented. The importance of mutual inductance in accurate modeling of parasitic inductance is established. New methods of modeling parasitic coupling and inductance for Electromigration (EM), Gate Oxide Reliability (GOR) and Negative Bias Threshold Instability (NBTI) are presented. Based on these methods, a new paradigm for reliability-driven physical design is proposed. Results of application of this research on large industrial designs are presented. This research clearly brings out the importance of accurate modeling and analysis to ensure first pass success of complex SOC designs.