Characterization of IC manufacturing process deformations using memory test results

Very deep sub-micron integrated circuit manufacturing is an expensive and technologically challenging endeavor, with top-of-the-line fabrication lines going into the billions of dollars in equipment cost and recent IC manufacturing process technologies reaching several hundreds of individual processing steps. It is therefore vital for successful manufacturing of any integrated circuit product to continuously scrutinize its status and to identify the most critical yield detractors.The research presented in this thesis is an investigation of the feasibility of a comprehensive framework for discovery, classification, and archiving of process deformations in modern integrated circuit manufacturing processes based on extensive analyses of memory test results. The use of such a framework as a means of rigorous development and maintenance of continuously updated portfolios of product-independent deformation characteristics of the investigated manufacturing process is demonstrated in detail.A thorough description of the implementation of such a framework is presented and its feasibility is demonstrated and confirmed based on its experimental application to large sets of memory test data collected from two modern SRAM and DRAM memory products.Process-induced deformations are key contributors of the overall yield loss of an integrated circuit product. As new and more complex failure mechanisms emerge due to the rapidly growing complexity of future process technologies and shrinking feature sizes, it becomes continuously more crucial to have a rigorous means to efficiently determine and characterize process deformations as accurately as possible in order to quantify and predict their impact on the manufacturing and product yield and to ultimately reach the targeted strategical yield objectives.