Research On Addressable Test Chip Design For Nanometer Integrated Circuits

As the main approach to extract parameters, assess processing tool performance, formulating layout design rules, detect or quantify random and systematic defects, establish product reliability, test chips play an important role in reducing process development cycle and improving manufacturing yield. However, the increasingly complicated processes of nano-era require a lot more test structures than the amount that traditional test chips can accommodate. Under such a circumstance, addressable test chips emerge as the solution and become a hot research area. We have focused on this area and the main content of the thesis is the design methodology of high-density and high-accuracy addressable test chips. Next is a summary of our research contents and innovations:Proposed an large-scale addressable test chip design scheme for process defects detection during the development of a new technology node. In our design, we make all the test structures four-terminal connected and implement the switch by thick-oxide NMOS transistor, thus improve the design of addressable test chip on measurement accuracy, array size as well as area efficiency. This design scheme has been verified by a64X64large-scale test chip in a65nm CMOS technology node. And also it has strong universality and can be well transferred to another technology node.Expanded the application of the above design scheme to the fault location of failure analysis. Manual probing system fails to provide enough probes to perform fault location techniques. Another group of PADs are added, and all the test structures can share these PADs. Only three PADs are needed for each fault location, which make the fault location techniques feasible by using manual probing system. This specialized design scheme has been verified in a110nm CMOS technology node.Applied the first mentioned design scheme for process defects detection during the process stage of mass production. A suitable layout design method is proposed to implement the design scheme in the limited space of scribe line. The whole layout is divided into several modules with separate design, and the design of the module is customized to some types. Such layout design method simplifies the work of the design, and makes it possible that the layout is highly automation, well extensibility and also easy to be transferred to another technology node. This layout design method has been verified in a45nm CMOS technology node.Proposed a MOS transistor array design scheme for characterization and modeling of statistical variations in MOSFET characteristics. The proposed array achieves both compact layout area with240devices placed in scribe line and accurate measurement of saturation region current, sub-threshold current, sub-threshold voltage and gate leakage. Also to reduce the testing cycle, the array has been implemented with two levels of metal. This design scheme has been verified in a28nm CMOS technology node.